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? copyright 1998 advanced micro devices, inc. all rights reserved. advanced micro devices, inc. (amd) reserves the right to discontinue its products, or make changes in its products, at any ti me without notice. the information in this publication is believed to be accurate at the time of publication, but amd makes no representations or warranties with respect to the accuracy or completeness of the contents of this publication or the information contained herein, and reserves the right to make changes at any time, without n otice. amd disclaims responsibility for any consequences resulting from the use of the information included in this publication. this publication neither states nor implies any representations or warranties of any kind, including but not limited to, any im plied warranty of merchantability or fitness for a particular purpose. amds products are not designed, intended, authorized or warranted for use as components in systems intended for surgical impla nt into the body, or in other applications intended to support or sustain life, or in any other application in which the failure of amds product could create a situation where personal inju ry, death, or severe property or environmental damage may occur. amd assumes no liability whatsoever for claims associated with the sale or use (including the use of engineering samples) of amd products except as provided in amds terms and conditions of sale for such product. publication# 21028 rev: b amendment/ 0 issue date: december 1998 lan?sc400 and lansc410 single-chip, low-power, pc/at-compatible microcontrollers distinctive characteristics lan?sc400 and lansc410 microcontrollers n e86 tm family of x86 embedded processors C offers improved time-to-market, software migration, and field-proven development tools n highly integrated single-chip cpu with a complete set of common peripherals C accelerates time-to-market with simplified hardware C low-power 0.35-micron process technology C single chip delivers smallest system form factor C 33-mhz, 66-mhz, and 100-mhz operating frequencies n am486 ? cpu core C robust microsoft ? windows ? compatible cpu C 8-kbyte write-back cache for enhanced performance C fully static design with system management mode (smm) for power savings n comprehensive power management unit C seven modes of operation allow fine-tuning of power requirements for maximum battery life C provides a superset of apm 1.2 features n glueless burst-mode rom/flash memory/sram interface C reduces system cost by allowing mask rom and flash memory at the same time with three rom/ flash memory/sram chip selects n glueless dram controller C allows mixed dram types on a per-bank basis to reduce system cost n vesa local (vl) bus and isa bus interface C reduces time-to-market with a wide variety of off- the-shelf companion chips n standard pc/at system logic (pics, dmacs, timer, rtc) C dos, rom-dos, windows, and industry- standard bios support C leverages the benefits of desktop computing environment at embedded price points n bidirectional parallel port with enhanced parallel port (epp) mode n 16550-compatible uart n infrared port for wireless communication C standard and high-speed n keyboard interface C matrix keyboard support with up to 15 rows and 8 columns C scp-emulation mode for pc/at and xt keyboard support lansc400 microcontroller only the lansc400 microcontroller includes the following additional features designed specifically for mobile computing applications. the lansc410 microcontrol- ler does not include these features. n dual pc card (pcmcia version 2.1) controller supports 8- or 16-bit data bus C end-user (after-market) system expansion C exca-compliant, 82365-register set compatible C leverages off-the-shelf card and socket services C supports dma transfers between i/o pc cards and system dram n lcd graphics controller C supports monochrome and 4-bit color super twisted nematic (stn) lcds C unified memory architecture (uma) eliminates separate video memory
2 lan?sc400 and lansc410 microcontrollers data sheet general description the lan?sc400 and lansc410 microcontrollers are the among the latest in a series of e86? family microcontrollers, which integrate proven x86 cpu cores with a comprehensive set of on-chip peripherals in a 0.35-micron process. the lansc400 and lansc410 microcontrollers combine a 32-bit, low-voltage am486 cpu with a complete set of pc/at-compatible peripherals, along with the power management features required for battery operation. leveraging the benefits of the x86 desktop computing environment, the lansc400 and lansc410 microcon- trollers integrate all of the common logic and i/o func- tionality associated with a pc/at computing system into a single device, eliminating the need for multiple periph- eral chips. fully integrated pc/at-compatible peripher- als include two 8259a-compatible programmable interrupt controllers (pics), two 8237a-compatible dma controllers, an 8254-compatible timer, a 16550 uart, an irda controller, vl-bus and isa bus controllers, a real-time clock (rtc), and enhanced parallel port (epp) mode for the parallel port. with its low-voltage am486 ? cpu core and ultra-small form factor, the lansc400 microcontroller is highly op- timized for mobile computing applications. the lansc410 microcontroller is targeted specifically for embedded systems. a feature comparison of the two microcontrollers is shown in table 1 on page 3. the lansc400 and lansc410 microcontrollers use the industry-standard 486 microprocessor instruction set. all software written for the x86 architecture family is compatible with the lansc400 and lansc410 microcontrollers. the lansc400 and lansc410 microcontrollers are based on a fully static design and include an advanced power management unit. operating voltages are 2.7 vC3.3 v with 5-v-tolerant i/o pads. orderable in both 33-mhz, 66-mhz, and 100-mhz peak processor speeds, the product is available in the ultra-small 292 ball grid array (bga) package. ordering information amd standard products are available in several packages and operating ranges. the order number (valid combination) is formed by a combination of the elements below. valid combinations valid combinations list configurations planned to be supported in volume for this device. consult the local amd sales office to confirm availability of specific valid combinations and to check on newly released combinations. C33 a c temperature range c = commercial for 33 and 66 mhz: t case = 0 c to +95 c for 100 mhz: t case = 0 c to +85 c i = industrial for 33 and 66 mhz, t case = C 40 c to +95 c package type a = 292-pin bga (ball grid array) speed option C33 = 33 mhz C66 = 66 mhz C100 = 100 mhz elansc400 device number/description lansc400 microcontroller lansc410 microcontroller valid combinations elansc400C33 ac, ai elansc400C66 elansc400C100 ac elansc410C33 ac, ai elansc410C66 elansc410C100 ac
lan?sc400 and lansc410 microcontrollers data sheet 3 table 1. product compari sonlansc400 and lansc410 microcontrollers feature lansc410 lansc400 core cpu l1 cache system management mode (smm) floating-point unit am486 cpu 8-kbyte write-back yes no am486 cpu 8-kbyte write-back yes no data bus 16, 32 bit 16, 32 bit isa interface isa bus mastering 8, 16 bit no 8, 16 bit no vesa local bus vl bus mastering 32 bit no 32 bit no power management mode timers activity detection smi/nmi generation battery monitoring yes yes yes yes yes yes yes yes yes yes on-chip rom interface width size (total rom space) rom chip selects burst-mode support support for sram as rom address space 8, 16, 32 bit 3 x 64 mbyte 3 yes yes 8, 16, 32 bit 3 x 64 mbyte 3 yes yes on-chip dram controller banks width size (total of all banks) edo support support for sram as main memory 4 16, 32 bit 64 mbyte yes rom-mappable 4 16, 32 bit 64 mbyte yes rom-mappable integrated pc/at-compatible peripherals programmable timer (8254-compatible) real-time clock (146818a-compatible) port b and port 92h i/o registers cascaded dma controllers (8237a) width total number of channels external channels cascaded interrupt controllers (8259) external irq signals yes yes yes 2 8, 16 bit 7 2 2 8 yes yes yes 2 8, 16 bit 7 2 2 8 bidirectional parallel port with epp mode yes yes serial port (uart) 16550-compatible 16550-compatible keyboard interface support for external 8042 scp xt interface matrix scanned with scp emulation yes yes yes yes yes yes general-purpose input/output signals 32 32 infrared (irda) port yes yes pc card controller sockets pcmcia 2.1-compliant 82365-compatible no yes 2 yes yes lcd graphics controller programmable clock frequency unified memory architecture (uma) no yes yes yes jtag support yes yes pin count and package 292 bga 292 bga v cc : cpu core on-chip peripheral logic i/o tolerance (designated pins) 2.7C3.3 v 3.3 v 5 v 2.7C3.3 v 3.3 v 5 v processor clock rate 33, 66, 100 mhz 33, 66, 100 mhz
4 lan?sc400 and lansc410 microcontrollers data sheet block diagramlansc400 microcontroller serial port infrared graphics or local bus controller socket a ctrl gpios or parallel port or pc card socket b 32-khz crystal clock i/o gpios gpios columns or xt keyboard dram control addr addr gpios gpios internal bus system address bus data rom control data bus gpios or keyboard rows dram control or keyboard rows isa control or keyboard rows isa control isa control or gpios gpios am486 ? cpu dual dma controllers 8237 power management unit clock generation real-time clock boundary scan at port logic timer 8254 dual interrupt controllers 8259 pc card controller epp parallel port uart 16550 infrared port memory management unit address decoder data steering lcd graphics controller local bus controller system arbiter memory controller keyboard interface: matrix/xt/scp isa bus controller lansc400 microcontroller
lan?sc400 and lansc410 microcontrollers data sheet 5 block diagramlansc410 microcontroller system arbiter serial port infrared local bus controller gpios or parallel port 32-khz crystal clock i/o gpios gpios columns or xt keyboard dram control addr addr gpios gpios internal bus system address bus data rom control data bus gpios or keyboard rows dram control or keyboard rows isa control or keyboard rows isa control isa control or gpios gpios am486 ? cpu dual dma controllers 8237 power management unit clock generation real-time clock boundary scan at port logic timer 8254 dual interrupt controllers 8259 epp parallel port uart 16550 infrared port memory management unit address decoder data steering local bus controller memory controller keyboard interface: matrix/xt/scp isa bus controller lansc410 microcontroller
6 lan?sc400 and lansc410 microcontrollers data sheet logic symbollansc400 microcontroller dram, vl, rom, isa and pc card data scan keyboard rows/isa interface gpio/isa interface gpio/external buffer control sa25Csa0 sd15Csd0 [d31Cd16] romrd romcs1 Cromcs0 ior iow memr memw rstdrv lcdd0 [vl_rst ] m [vl_be2 ] lc [vl_be1 ] sck [vl_be0 ] frm [vl_lclk] lvee [vl_brdy ] lvdd [vl_blast ] dtr , rts , sout cts , dcd , dsr rin , sin sirout sirin acin bl2 Cbl1 bl0 [clk_io] gpio_cs0 gpio_cs1 gpio_cs2 [[dbufrdl ]] gpio_cs3 [[dbufrdh ]] gpio_cs4 [[dbufoe ]] gpio_cs5 [iocs16 ] gpio_cs6 [iochrdy] gpio_cs7 [pirq1] gpio_cs8 [pirq0] ma11Cma5 d15Cd0 ras1 Cras0 casl/h1 Ccasl/h0 mwe rst_a [[bndscn_tdi]] reg_a [[bndscn_tdo]] cd_a rdy_a bvd1_a, bvd2_a wait_ab oe we icdir wp_a gpio31 [strb ] [mcel_b ] gpio30 [afdt ] [mceh_b ] gpio29 [slctin ] [rst_b] gpio28 [init ] [reg_b ] gpio27 [error ] [cd_b ] gpio26 [pe] [rdy_b ] gpio25 [ack ] [bvd1_b] gpio24 [busy] [bvd2_b] gpio23 [slct] [wp_b] gpio22 [ppoen ] gpio21 [ppdwe ] 32kxtal1, 32kxtal2 lf_int, lf_ls reset bbatsen spkr bndscn_en v cc _rtc gpio_cs9 [tc] gpio_cs10 [aen] gpio_cs11 [pdack0 ] lcdd1 [vl_ads ] lcdd2 [vl_w/r ] lcdd3 [vl_m/io ] lcdd4 [vl_lrdy ] lcdd5 [vl_d/c ] lcdd6 [vl_ldev ] lcdd7 [vl_be3 ] sus_res / kbd_row14 gpio_cs12 [pdrq0] ma4 ma3 {cfg3} ma2 {cfg2} ma1 {cfg1} ma0 {cfg0} kbd col1-0 [xt_clk/data] kbd_row13 [[r32bfoe ]] romwr mcel_a [[bndscn_tck]] mceh_a [[bndscn_tms]] lf_vid, lf_hs gpio_cs13 [pcma_v cc ] gpio_cs14 [pcma_vpp1] gpio15 [pcma_vpp2] gpio16 [pcmb_v cc ] gpio17 [pcmb_vpp1] gpio18 [pcmb_vpp2] gpio19 [lbl2 ] gpio20 [cd_a2 ] kbd_col7 kbd_col6-2 / pirq7-3 kbd_row12 [mcs16 ] kbd_row11 [sbhe ] kbd_row10 [bale] kbd_row9 [pirq2] kbd_row8 [pdrq1] kbd_row7 [pdack1 ] kbd_row6 [ma12] kbd_row5 [ras3 ] kbd_row4 [ras2 ] kbd_row3 [cash3 ] kbd_row2 [cash2 ] kbd_row1 [casl3 ] kbd_row0 [casl2 ] lcd graphics controller or vesa local bus 8-pin serial port dram interface and feature configuration pins infrared interface boundary scan enable speaker rtc reset loop filters power management interface gpios gpio/pc card power control scan keyboard columns/irqs/xt keyboard interface scan keyboard rows/dram interface vl, rom, isa, and pc card address rom/flash memory control pc card command isa bus command and reset dedicated single slot pc card and boundary scan interface parallel port or second pc card or gpios 32-khz crystal lansc400 microcontroller 292 bga notes: / =two functions available on the pin at the same time. { } = function during hardware reset. [ ] = alternative function selected by firmware configuration. [[ ]] = alternate function selected by a hardware configuration pin state at power-on reset. this does not apply to [[bndscn_tck]], [[bndscn_tms]], [[bndscn_tdi]], and [[bndscn_tdo]]. these alternate functions are enabled by the bndscn_en signal.
lan?sc400 and lansc410 microcontrollers data sheet 7 logic symbollansc410 microcontroller dram, vl, rom, and isa data scan keyboard rows/isa interface gpio/isa interface gpio/external buffer control sa25Csa0 sd15Csd0 [d31Cd16] romrd romcs1 Cromcs0 ior iow memr memw rstdrv vl_rst vl_be2 vl_be1 vl_be0 vl_lclk vl_brdy vl_blast dtr , rts , sout cts , dcd , dsr rin , sin sirout sirin acin bl2 Cbl1 bl0 [clk_io] gpio_cs0 gpio_cs1 gpio_cs2 [[dbufrdl ]] gpio_cs3 [[dbufrdh ]] gpio_cs4 [[dbufoe ]] gpio_cs5 [iocs16 ] gpio_cs6 [iochrdy] gpio_cs7 [pirq1] gpio_cs8 [pirq0] ma11Cma5 d15Cd0 ras1 Cras0 casl/h1 Ccasl/h0 mwe [[bndscn_tdi]] [[bndscn_tdo]] gpio31 [strb ] gpio30 [afdt ] gpio29 [slctin ] gpio28 [init ] gpio27 [error ] gpio26 [pe] gpio25 [ack ] gpio24 [busy] gpio23 [slct] gpio22 [ppoen ] gpio21 [ppdwe ] 32kxtal1, 32kxtal2 lf_int, lf_ls reset bbatsen spkr bndscn_en v cc _rtc gpio_cs9 [tc] gpio_cs10 [aen] gpio_cs11 [pdack0 ] vl_ads vl_w/r vl_m/io vl_lrdy vl_d/c vl_ldev vl_be3 sus_res / kbd_row14 gpio_cs12 [pdrq0] ma4 ma3 {cfg3} ma2 ma1 {cfg1} ma0 {cfg0} kbd col1-0 [xt_clk/data] kbd_row13 [[r32bfoe ]] romwr [[bndscn_tck]] [[bndscn_tms]] lf_hs gpio_cs13 gpio_cs14 gpio15 gpio16 gpio17 gpio18 gpio19 [lbl2 ] gpio20 kbd_col7 kbd_col6-2 / pirq7-3 kbd_row12 [mcs16 ] kbd_row11 [sbhe ] kbd_row10 [bale] kbd_row9 [pirq2] kbd_row8 [pdrq1] kbd_row7 [pdack1 ] kbd_row6 [ma12] kbd_row5 [ras3 ] kbd_row4 [ras2 ] kbd_row3 [cash3 ] kbd_row2 [cash2 ] kbd_row1 [casl3 ] kbd_row0 [casl2 ] vesa local bus 8-pin serial port dram interface and feature configuration pins infrared interface boundary scan enable speaker rtc reset loop filters power management interface gpios gpio/ power control scan keyboard columns/irqs/xt keyboard interface scan keyboard rows/dram interface vl, rom, and isa address rom/flash memory control isa bus command and reset boundary scan interface parallel port or gpios 32-khz crystal lansc410 microcontroller 292 bga notes: / =two functions available on the pin at the same time. { } = function during hardware reset. [ ] = alternative function selected by firmware configuration. [[ ]] = alternate function selected by a hardware configuration pin state at power-on reset. this does not apply to [[bndscn_tck]], [[bndscn_tms]], [[bndscn_tdi]], and [[bndscn_tdo]]. these functions are enabled by the bndscn_en signal.
8 lan?sc400 and lansc410 microcontrollers data sheet table of contents distinctive characteristics ................................................................................................... ......... 1 lan?sc400 and lansc410 microcontrollers ...................................................................... 1 lansc400 microcontroller only ............................................................................................. 1 general description ........................................................................................................... .......... 2 block diagramlansc400 microcontroller .............................................................................. 4 block diagramlansc410 microcontroller .............................................................................. 5 logic symbollansc400 microcontroller ................................................................................. 6 logic symbollansc410 microcontroller ................................................................................. 7 related amd products .......................................................................................................... .... 12 e86? family devices ........................................................................................................... 12 related documents ............................................................................................................. .. 12 lan?sc400 microcontroller evaluation board ................................................................... 13 third-party development support products ...................................................................................13 customer service .............................................................................................................. .... 13 architectural overview ........................................................................................................ ....... 13 low-voltage am486 cpu core ............................................................................................ 14 power management .............................................................................................................. 14 clock generation .............................................................................................................. .... 14 rom/flash memory interface ............................................................................................... 15 dram controller ............................................................................................................... .... 15 integrated standard pc/at peripherals ................................................................................ 15 pc/at support features ....................................................................................................... 1 6 bidirectional enhanced parallel port (epp) .......................................................................... 16 serial port .................................................................................................................... .......... 17 keyboard interfaces ........................................................................................................... ... 17 programmable general-purpose inputs and outputs ........................................................... 17 infrared port for wireless communication ............................................................................ 17 dual pc card controller (lansc400 microcontroller only) ................................................. 17 graphics controller for cga-compatible text and graphics (lansc400 microcontroller only) .. 17 jtag test features ............................................................................................................ .. 18 system interfaces ............................................................................................................. .... 18 system considerations ......................................................................................................... ..... 20 connection diagramlansc400 and lansc410 microcontrollers ........................................ 24 pin designations .............................................................................................................. .......... 25 pin naming .................................................................................................................... ........ 25 pin changes for the lansc410 microcontroller ....................................................................... 25 pin designations (pin number)lansc400 microcontroller ................................................... 26 pin designations (pin name)lansc400 microcontroller ...................................................... 29 pin designations (pin number)lansc410 microcontroller ................................................... 33 pin designations (pin name)lansc410 microcontroller ...................................................... 36 pin state tables .............................................................................................................. .......... 40 pin characteristics ........................................................................................................... ..... 40 using the pin state tables .................................................................................................... 41 signal descriptions ........................................................................................................... ......... 62 multiplexed pin function options .......................................................................................... 70 using the configuration pins to select pin functions............................................................ 74 clocking ...................................................................................................................... ............... 76 clock generation .............................................................................................................. .... 76 integrated peripheral clock sources .................................................................................... 77 32-khz crystal oscillator ..................................................................................................... .. 79 loop filters .................................................................................................................. ......... 79 intermediate and low-speed plls ....................................................................................... 79 graphics dot clock pll (lansc400 microcontroller only) ................................................. 80
lan?sc400 and lansc410 microcontrollers data sheet 9 high-speed pll ................................................................................................................ .... 81 band gap block ................................................................................................................ .... 81 rtc voltage monitor ........................................................................................................... .. 81 clock specifications .......................................................................................................... .... 83 absolute maximum ratings ...................................................................................................... .86 operating ranges .............................................................................................................. ........ 86 dc characteristics over commercial and industrial operating ranges .................................... 86 capacitance ................................................................................................................... ............ 87 typical power numbers ......................................................................................................... .... 88 power requirements under different power management modes ...................................... 88 derating curves ............................................................................................................... .......... 89 ac switching characteristics and waveforms .......................................................................... 91 key to switching waveforms ................................................................................................ 91 ac switching test waveforms .................................................................................................. 9 1 ac switching characteristics over commercial and industrial operating ranges ............... 92 thermal characteristics ....................................................................................................... .... 130 physical dimensionsbga 292plastic ball grid array ...................................................... 131 list of figures figure 1. typical mobile terminal design ............................................................................. 21 figure 2. system diagram with trade-offslansc400 microcontroller ............................. 22 figure 3. system design with trade-offslansc410 microcontroller ............................... 23 figure 4. clock generation block diagram ........................................................................... 76 figure 5. clock source block diagram ................................................................................. 78 figure 6. 32-khz crystal circuit ............................................................................................ 79 figure 7. 32-khz oscillator circuit ........................................................................................ 79 figure 8. intermediate and low-speed plls block diagram ............................................... 80 figure 9. graphics dot clock pll block diagram ................................................................ 81 figure 10. high-speed pll block diagram ............................................................................ 82 figure 11. rtc voltage monitor circuit .................................................................................. 82 figure 12. timing diagram for rtc-on power-down sequence ........................................... 83 figure 13. pll enabling timing sequence ............................................................................ 85 figure 14. 3.3-v i/o drive type a rise time ......................................................................... 89 figure 15. 3.3-v i/o drive type a fall time ........................................................................... 89 figure 16. 3.3-v i/o drive type b rise time ......................................................................... 89 figure 17. 3.3-v i/o drive type b fall time ........................................................................... 89 figure 18. 3.3-v i/o drive type c rise time ......................................................................... 90 figure 19. 3.3-v i/o drive type c fall time ........................................................................... 90 figure 20. 3.3-v i/o drive type d rise time ......................................................................... 90 figure 21. 3.3-v i/o drive type d fall time ........................................................................... 90 figure 22. 3.3-v i/o drive type e rise time ......................................................................... 90 figure 23. 3.3-v i/o drive type e fall time ........................................................................... 90 figure 24. power-up timing sequence .................................................................................. 92 figure 25. fast mode 8-/16-/32-bit rom/flash memory read cycle .................................... 94 figure 26. fast mode cpu read of three consecutive bytes from 8-bit rom/flash memory .. 95 figure 27. fast mode 8-/16-/32-bit flash memory write cycles ............................................ 95 figure 28. fast mode 16-bit burst rom read cycles ........................................................... 96 figure 29. fast mode cpu burst read from 32-bit burst mode rom/flash memory ........... 96 figure 30. normal mode 8-/16-bit rom/flash memory read cycles .................................... 97 figure 31. normal mode 8-/16-bit flash memory write cycles .............................................. 97 figure 32. dram page hit read, interleaved ........................................................................ 99 figure 33. dram page hit write, interleaved ........................................................................ 99 figure 34. dram page miss read, interleaved ................................................................... 100
10 lan?sc400 and lansc410 microcontrollers data sheet figure 35. dram page hit read, non-interleaved .............................................................. 100 figure 36. dram page hit write, non-interleaved .............................................................. 101 figure 37. dram page miss read, non-interleaved ........................................................... 101 figure 38. edo dram page hit read, non-interleaved ..................................................... 102 figure 39. edo dram page miss read, non-interleaved .................................................. 102 figure 40. dram cas -before-ras refresh ........................................................................ 103 figure 41. dram self-refresh ............................................................................................. 103 figure 42. dram slow refresh ............................................................................................ 104 figure 43. 8-bit isa bus cycles ............................................................................................ 107 figure 44. 16-bit isa bus cycles .......................................................................................... 108 figure 45. isa dma read cycle .......................................................................................... 109 figure 46. isa dma write cycle ........................................................................................... 110 figure 47. vesa local bus cycles ....................................................................................... 112 figure 48. epp parallel port write cycle .............................................................................. 114 figure 49. epp parallel port read cycle ............................................................................. 115 figure 50. i/o decode (r/w), address decode only ........................................................... 116 figure 51. i/o decode (r/w), command qualified .............................................................. 116 figure 52. i/o decode (r/w), gpio_csx as 8042cs timing .............................................. 117 figure 53. memory cs decode (r/w), address decode only ............................................. 117 figure 54. memory cs decode (r/w), command qualified ................................................ 118 figure 55. pc card attribute memory read cycle (lansc400 microcontroller only) ........ 120 figure 56. pc card attribute memory write cycle (lansc400 microcontroller only) ......... 121 figure 57. pc card common memory read cycle (lansc400 microcontroller only) ....... 122 figure 58. pc card common memory write cycle (lansc400 microcontroller only) ....... 123 figure 59. pc card i/o read cycle ...................................................................................... 124 figure 60. pc card i/o write cycle ...................................................................................... 125 figure 61. pc card dma read cycle (memory read to i/o write) ..................................... 126 figure 62. pc card dma write cycle (i/o read to memory write) ..................................... 127 figure 63. graphics panel interface timing (lansc400 microcontroller only) ................... 128 figure 64. graphics panel power sequencing (lansc400 microcontroller only) .............. 129 list of tables table 1. product comparisonlansc400 and lansc410 microcontrollers ...................... 3 table 2. drive output description ........................................................................................ 40 table 3. pin type abbreviations .......................................................................................... 40 table 4. power pin type abbreviations ............................................................................... 41 table 5. power-down groups ............................................................................................. 41 table 6. pin state tablesystem interface ........................................................................ 42 table 7. pin state tablememory interface ....................................................................... 44 table 8. pin state tablegpios/parallel port/pc card socket b ..................................... 47 table 9. pin state tablegpios/isa bus .......................................................................... 49 table 10. pin state tablegpios/system data (sd) buffer control ................................... 51 table 11. pin state tablegpios ........................................................................................ 52 table 12. pin state tableserial port .................................................................................. 52 table 13. pin state tableinfrared interface ....................................................................... 52 table 14. pin state tablekeyboard interface .................................................................... 53 table 15. pin state tablepc card socket a ..................................................................... 55 table 16. pin state tablegraphics controller/vesa local bus control ............................ 56 table 17. pin state tablemiscellaneous ............................................................................ 58 table 18. pin state tablepower and ground .................................................................... 59 table 19. signal description table ........................................................................................ 62 table 20. multiplexed pin configuration options ................................................................... 70 table 21. pinstrap bus buffer options .................................................................................. 74
lan?sc400 and lansc410 microcontrollers data sheet 11 table 22. cfg0 and cfg1 configuration ............................................................................. 74 table 23. cfg2 configuration (lansc400 microcontroller only) ......................................... 74 table 24. cfg3 configuration ............................................................................................... 75 table 25. bndscn_en configuration .................................................................................. 75 table 26. integrated peripheral clock sources ..................................................................... 77 table 27. frequency selection control for graphics dot clock pll ..................................... 80 table 28. loop-filter component specification for plls ...................................................... 84 table 29. analog v cc (vcca) specification ......................................................................... 84 table 30. 32.768-khz crystal characteristics ....................................................................... 84 table 31. start-up time specifications plls ........................................................................ 84 table 32. pll jitter specification .......................................................................................... 85 table 33. operating voltage (commercial and industrial) ..................................................... 87 table 34. power estimates .................................................................................................... 88 table 35. power-on reset cycle .......................................................................................... 92 table 36. rom/flash memory cycles ................................................................................... 93 table 37. dram cycles ........................................................................................................ 98 table 38. isa cycles ........................................................................................................... 105 table 39. vesa local bus cycles ....................................................................................... 111 table 40. parallel port cycles ............................................................................................. 113 table 41. general-purpose input/output cycles ................................................................. 115 table 42. pc card cycleslansc400 microcontroller only ............................................ 119 table 43. pc card attribute memory read function (lansc400 microcontroller only) .... 120 table 44. pc card attribute memory write function (lansc400 microcontroller only) .... 121 table 45. pc card common memory read function (lansc400 microcontroller only) .. 122 table 46. pc card common memory write function (lansc400 microcontroller only) ... 123 table 47. pc card i/o read function (lansc400 microcontroller only) .......................... 124 table 48. pc card i/o write function (lansc400 microcontroller only) .......................... 125 table 49. pc card dma read function (lansc400 microcontroller only) ....................... 126 table 50. pc card dma write function (lansc400 microcontroller only) ....................... 127 table 51. lcd graphics controller cycleslansc400 microcontroller only ................... 128 table 52. thermal resistance y j-t and q ja (c/w) for the 292-bga package) ................. 130 table 53. maximum t a at various airflows in c ................................................................ 130
12 lan?sc400 and lansc410 microcontrollers data sheet related amd products e86 ? family devices device description 80c186 16-bit microcontroller 80c188 16-bit microcontroller with 8-bit external data bus 80l186 low-voltage, 16-bit microcontroller 80l188 low-voltage, 16-bit microcontroller with 8-bit external data bus am186?em high-performance, 80c186-compatible, 16-bit embedded microcontroller am188?em high-performance, 80c188-compatible, 16-bit embedded microcontroller with 8-bit external data bus am186emlv high-performance, 80c186-compatible, low-voltage, 16-bit embedded microcontroller am188emlv high-performance, 80c188-compatible, low-voltage, 16-bit embedded microcontroller with 8-bit external data bus am186es high-performance, 80c186-compatible, 16-bit embedded microcontroller am188es high-performance, 80c188-compatible, 16-bit embedded microcontroller with 8-bit external data bus am186eslv high-performance, 80c186-compatible, low-voltage, 16-bit embedded microcontroller am188eslv high-performance, 80c188-compatible, low-voltage, 16-bit embedded microcontroller with 8-bit external data bus am186ed high-performance, 80c186- and 80c188-compatible, 16-bit embedded microcontroller with 8- or 16-bit external data bus am186edlv high-performance, 80c186- and 80c188-compatible, low-voltage, 16-bit embedded microcontroller with 8- or 16-bit external data bus am186er high-performance, 80c186-compatible, low-voltage, 16-bit embedded microcontroller with 32 kbyte of internal ram am188er high-performance, 80c188-compatible, low-voltage, 16-bit embedded microcontroller with 8-bit external data bus and 32 kbyte of internal ram am186cc high-performance, 80c186-compatible 16-bit embedded communications controller am186ch high-performance, 80c186-compatible 16-bit embedded hdlc microcontroller am186cu high-performance, 80c186-compatible 16-bit embedded usb microcontroller lan?sc300 high-performance, highly integrated, low-voltage, 32-bit embedded microcontroller lansc310 high-performance, single-chip, 32-bit embedded pc/at microcontroller lansc400 single-chip, low-power, pc/at-compatible microcontroller lansc410 single-chip, pc/at-compatible microcontroller am386?dx high-performance, 32-bit embedded microprocessor with 32-bit external data bus am386?sx high-performance, 32-bit embedded microprocessor with 16-bit external data bus am486?dx high-performance, 32-bit embedded microprocessor with 32-bit external data bus related documents the following documents provide additional information regarding the lansc400 and lansc410 microcontrollers. n lansc400 and lansc410 users manual , order #21030 n lansc400 register set reference manual , order #21032 n lansc400 register set reference manual amendment , order #21032a/1 n lansc400 evaluation board users manual , order #21906 n lansc400 microcontroller and windows ce m force demonstration system users manual , order #21892 n romcs0 redirection to pc card socket a on the lansc400 microcontroller application note , order #21643
lan?sc400 and lansc410 microcontrollers data sheet 13 lan ? sc400 microcontroller evaluation board the lan?sc400 microcontroller evaluation board is a stand-alone evaluation platform for the lansc400 and lansc410 microcontrollers. as a test and development platform for designs based on the lansc400 and lansc410 microcontrollers, this amd product is used by system designers to ex- periment with design trade-offs, make power measure- ments, and develop software. contact your local amd sales office for more information on evaluation board availability and pricing. third-party development support products the fusione86 sm program of partnerships for application solutions provides the customer with an array of products designed to meet critical time-to- market needs. products and solutions available from the amd fusione86 partners include protocol stacks, emulators, hardware and software debuggers, board- level products, and software development tools, among others. in addition, mature development tools and applications for the x86 platform are widely available in the general marketplace. customer service the amd customer service network includes u.s. offices, international offices, and a customer training center. expert technical assistance is available from the amd worldwide staff of field application engineers and factory support staff to answer e86? and comm86? family hardware and software development questions. hotline and world wide web support for answers to technical questions, amd provides e-mail support as well as a toll-free number for direct access to our corporate applications hotline. the amd world wide web home page provides the latest product information, including technical information and data on upcoming product releases. in addition, epd codekit software on the web site provides tested source code example applications. additional contact information is listed on the back of this datasheet. for technical support questions on all e86 and comm86 products, send e-mail to epd.support@amd.com . world wide web home page to access the amd home page, go to: www.amd.com . then follow the embedded processors link for information about e86 and comm86 products. questions, requests, and input concerning amds www pages can be sent via e-mail to webmaster@amd.com . documentation and literature free information such as data books, users manuals, data sheets, application notes, the e86? family products and development tools cd , order #21058, and other literature is available with a simple phone call. internationally, contact your local amd sales office for product literature. additional contact information is listed on the back of this data sheet. architectural overview the architectural goals of the lansc400 and lansc410 microcontrollers included a focus on cpu performance, cpu-to-memory performance, and inter- nal graphics controller (lansc400 microcontroller only) performance. the resulting architecture includes several distinguishing features of interest to the system designer: n the main system dram is shared between the cpu and graphics controller, so that the graphics controller can be serviced quickly to maintain video display performance at higher panel resolutions. the internal unified memory architecture (uma) implemented on the lansc400 and lansc410 microcontrollers means lower cost and less complication for the system designer, with only one dram interface, fewer pins, and a much smaller board for many designs. n cpu-to-memory performance is critical for both dram and rom accesses. the cpu on the lansc400 microcontroller has a concurrent path to the rom/flash memory interface and can execute code out of rom/flash memory at the same time as the graphics controller is accessing dram for a screen refresh. many system designs can take advantage of this concurrency without sacrificing performance. corporate applications hotline (800) 222-9323 toll-free for u.s. and canada 44-(0) 1276-803-299 u.k. and europe hotline literature ordering (800) 222-9323 toll-free for u.s. and canada (512) 602-5651 direct dial worldwide (512) 602-7639 fax
14 lan?sc400 and lansc410 microcontrollers data sheet n the rom/flash memory interface provides the flex- ibility to optimize the performance of rom cycles, including the support of burst-mode roms. this is beneficial because products based on the lansc400 and lansc410 microcontrollers may be implemented such that the operating system or application programs are executed from rom. n because the microcontrollers support a large num- ber of external buses and interfaces, the address and data buses are shared between the various in- terfaces to reduce pin count on the chip. these features result in a versatile architecture that can use various combinations of data bus sizes to achieve cost and performance goals. the architecture provides maximum performance and flexibility for high- end vertical applications, but contains functionality for a wider horizontal market that may demand less performance. n a typical lower performance/lower cost system might implement 16-bit dram banks, an 8-bit isa bus, an 8/16-bit pc card bus, and use the internal graphic controller. n a higher performance, full-featured system might include 32-bit dram, vl-bus to an external graph- ics controller, and a 16-bit isa/pc card bus. the following basic data bus configuration rules apply. (a complete list of feature trade-offs to be considered in system design can be found in system consider- ations on page 20.) n when the internal graphics controller on the lansc400 microcontroller is enabled, dram is al- ways 16 bits wide, and no 32-bit targets are sup- ported. this is because the graphics controller needs a guaranteed short latency for adequate video performance. if either 32-bit drams, 32-bit roms, or the vl-bus is enabled, the internal graph- ics controller is unavailable. note that, as a derivative of the original lansc400 mi- crocontroller, the lansc410 microcontroller shares the primary architectural characteristics of the lansc400 microcontroller described above, minus the graphics controller and pcmcia interfaces. the following sections provide an overview of the fea- tures of the lansc400 and lansc410 microcontrollers, including on-chip peripherals and system interfaces. low-voltage am486 cpu core the lansc400 and lansc410 microcontrollers are based on the low-voltage am486 cpu core. the core includes the following features: n 2.7C3.3-v operation reduces power consumption n industry-standard 8-kbyte unified code and data write-back cache improves both cpu and total sys- tem performance by significantly reducing traffic on the dram bus. n system management mode (smm) facilitates de- signs requiring power management by providing a mechanism to control power to unneeded peripher- als transparently to application software. to reduce power consumption, the floating-point unit has been removed from the am486 cpu core. float- ing-point instructions are not supported on the lansc400 and lansc410 microcontrollers, although normal software emulation can be easily implemented. the lansc400 and lansc410 microcontrollers use the industry-standard 486 instruction set. software written for the 486 microprocessor and previous mem- bers of the x86 architecture family can run on the lansc400 and lansc410 microcontrollers. power management power management on the lansc400 and lansc410 microcontrollers includes a dedicated power management unit and additional power man- agement features built into each integrated peripheral. the lansc400 and lansc410 microcontrollers can use the following techniques to conserve power: n slow down clocks when the system is not in active use n shut off clocks to parts of the chip that are idle n switch off power to parts of the system that are idle n automatically reduce power use when batteries are low the power management unit (pmu) controls stopping and changing clocks, smi generation, timers, activities, and battery-level monitoring. it provides: n hyper-speed, high-speed, low-speed, temporary low-speed, standby, suspend, and critical suspend modes n dynamically adjusted clock speeds for power reduction n programmable activity and wake-up monitoring n general-purpose i/o signals to control external devices and external power management n battery low and ac power monitoring n smi/nmi synchronization and generation clock generation the lansc400 and lansc410 microcontrollers re- quire only one 32.768-khz crystal to generate all the other clock frequencies required by the system. the output of the on-chip crystal oscillator circuit is used to generate the various frequencies by utilizing four phase-locked loop (pll) circuits (three for the lansc410 microcontroller). an additional pll in the cpu is used for hyper-speed mode.
lan?sc400 and lansc410 microcontrollers data sheet 15 rom/flash memory interface the integrated rom/flash memory interface supports the following features: n 8-, 16-, and 32-bit rom/flash memory interfaces n three rom/flash memory chip selects n burst-mode roms n rom accesses at both isa and cpu speeds (normal and fast-speed modes) n dedicated rom read and rom write signals for better performance each rom space can accommodate up to 64 mbyte of rom. the three rom spaces can be individually write- protected. this is useful for protecting code residing in flash memory devices. two of the three rom/flash memory chip selects can be remapped to a pc card socket via pinstrap or soft- ware control. this feature supports reprogramming of soldered-down flash memory boot devices and also simplifies testing of bios/xip os code. three rom access modes are supported: normal mode, fast mode, and burst mode. a different set of timings is used in each mode. in normal rom access mode, the bus cycles follow isa-like timings. in fast rom access mode, the bus cycle timing occurs at the cpu clock rate with controls for wait-state insertion. burst rom access timing is used when the rom/flash memory interface is fulfilling an internal cpu burst re- quest to support a cache line refill. wait states are supported for all rom and flash mem- ory accesses, including burst mode. burst-mode (page-mode) rom reads are supported for either a 16- or 32-bit rom interface running in fast mode. dram controller the integrated dram controller provides the signals and associated timing necessary to support an external dram array with minimal software programming and overhead. internal programmable registers are provided to select the dram type and operating mode, as well as refresh options. a wide variety of commodity drams are supported, and substantial flexibility is built into the dram controller to optimize performance of the cpu and (on the lansc400 microcontroller) the internal graphics control- ler, which uses system dram for its buffers. the dram controller supports the following features: n 3.3-v, 70-ns drams n up to four banks n 16-bit or 32-bit banks n up to 64 mbyte of total memory n self-refresh drams n fast page and extended data out (edo) drams n two-way interleaved operation among identically populated banks using fast-page mode devices n mixed depth and width of dram banks in non-inter- leaved mode n symmetrical and asymmetrical dram support integrated standard pc/at peripherals the lansc400 and lansc410 microcontrollers in- clude all the standard peripheral controllers that make up a pc/at system. dual dma controllers dual, cascaded, 8237a-compatible dma controllers provide seven user-definable dma channels. of the seven internal channels, four are 8-bit channels and three are 16-bit channels. channel 4 is used for the cas- cade function. any two of the seven channels can be mapped simul- taneously to external dma request/acknowledge lines. the dma controller on the lansc400 and lansc410 microcontrollers is software compatible with the pc/at cascaded 8237 controller pair. its features include: n single, block, and demand transfer modes n enable/disable channel controller n address increment or decrement n software priority n 64-mbyte system address space for increased performance n dynamic clock-enable design for reducing clocked elements during dma inactivity n programmable clock frequency for performance dual interrupt controllers dual, cascaded, 8259-compatible programmable interrupt controllers support 15 user-definable interrupt levels. eight external interrupt requests can be mapped to any of the 15 internal irq inputs. the interrupt controller block includes these features: n software-compatibility with pc/at interrupt controllers n 15-level priority controller n programmable interrupt modes n individual interrupt request mask capability n accepts requests from peripherals n resolves priority on pending interrupts and interrupts in service n issues interrupt request to processor n provides interrupt vectors for interrupt service routines n tied into the pmu for power management
16 lan?sc400 and lansc410 microcontrollers data sheet the interrupt controller block is functionally compatible with the standard cascaded 8259a controller pair as implemented in the pc/at system. the master control- ler drives the cpus interrupt input signal based on the highest priority interrupt request pending at the master controllers irq7Cirq0 inputs. the master irq2 input is configured for cascade mode and is driven only by the slave controllers interrupt output signal. the high- est pending interrupt at the slaves irq inputs will therefore drive the irq2 input of the master. the interrupt controller has programmable sources for interrupts that are controlled through extended config- uration registers and, on the lansc400 microcontrol- ler, through pc card controller configuration registers. programmable interval timer (pit) the programmable interval timer (pit) on the lansc400 and lansc410 microcontrollers is soft- ware-compatible with pc/at 8254 system timers. the pit provides three 16-bit counters that can be operated independently in six different modes. the pit is gener- ally used for timing external events, counting, and pro- ducing repetitive waveforms. the pit can be programmed to count in binary or in bcd. real-time clock (rtc) the rtc designed into the lansc400 and lansc410 microcontrollers is compatible with the mc146818a device used in pc/at systems. the rtc consists of a time-of-day clock with alarm interrupt and a 100-year calendar. the clock/calendar has a pro- grammable periodic interrupt, 114 bytes of static user ram, and can be represented in either binary or bcd. the rtc includes the following features: n counts seconds, minutes, and hours of the day n counts days of the week, date, month, and year n 12C24 hour clock with am and pm indication in 12-hour mode n 14 clock, status, and control registers n 114 bytes of general-purpose ram n three separately software-maskable and testable interrupts C time-of-day alarm is programmable to occur from once-per-second to once-per-day C periodic interrupts can be continued to occur at rates from 122 m s to 500 ms C update-ended interrupt provides cycle status n dedicated power pin directly supports lithium backup battery when the rest of the chip is com- pletely powered down (rtc-only mode) n voltage monitor circuit checks the voltage level of the lithium backup battery and sets a bit when the battery is below specification. n internal rtc reset signal performs a reset when power is applied to the rtc core. pc/at support features the lansc400 and lansc410 microcontrollers provide all of the support functions found in the original ibm pc/at. these include the port b status and control bits, speaker control, cpu-core reset based on the system control processor (scp), and a20 gate control, as well as extensions for fast cpu core reset. in addition, a cpu shutdown cycle (e.g., as a result of a triple fault) generates a cpu core reset. bidirectional enhanced parallel port (epp) the parallel port on the lansc400 and lansc410 microcontrollers is functionally compatible with ibm pc/at and ps/2 systems, with an added epp mode for faster transfers. the microcontrollers parallel port in- terface provides all the status inputs, control outputs, and the control signals necessary for the external par- allel port data buffers. the parallel port interface on both microcontrollers is shared with some of the gpio signals and, on the lansc400 microcontroller, with the second pc card socket interface. only one of these interfaces can be enabled at one time. the parallel port interface can be configured to operate in one of three different modes of operation: n pc/at compatible mode : this mode provides a byte-wide forward (host-to-peripheral) channel with data and status lines used according to their original (centronics) definitions in the ibm pc/at. n bidirectional mode : this mode offers byte-wide bi- directional parallel data transfers between host and peripheral, equivalent to the parallel interface on the ibm ps/2. n enhanced parallel port (epp) mode : this mode provides a byte-wide bidirectional channel con- trolled by the microcontroller. it provides separate address and data cycles over the eight data lines of the interface with an automatic address and data strobe for the address and data cycles, respectively. epp mode offers wider system bandwidth and in- creased performance over both the pc/at compat- ible and bidirectional modes.
lan?sc400 and lansc410 microcontrollers data sheet 17 serial port the lansc400 and lansc410 microcontrollers in- clude an industry-standard 16550a uart. the uart can be used to drive a standard 8-pin serial interface or a 2-pin infrared interface. the serial interface and infra- red interface signals are available on the lansc400 and lansc410 microcontrollers at all times, though only one is available at any given time. the uart powers up as a 16450-compatible device. it can be switched to and from the fifo (16550) mode under software control. in the fifo mode, the receive and the transmit circuitry are each enhanced by sepa- rate 16-byte fifos to off-load the cpu from repetitive service routines. the serial port includes the following features: n eight-pin interface: serial in, serial out, two modem control lines, and four modem status lines n separately enabled receiver line status, receiver data, character timeout, transmitter holding register, and modem status interrupts n baud-rate generator provides input clock divisor from 1 to 65535 to create 16x clock n 5-, 6-, 7-, or 8-bit data n even, odd, stick, or no parity generation and checking n 1, 1-1/2 or 2 stop-bit generation n break generation/detection keyboard interfaces the integrated keyboard controller has the following features: n matrix keyboard support with up to 15 rows and 8 columns n hardware support for software emulation of the system control processor (scp) emulation logic n xt keyboard interface programmable general-purpose inputs and outputs the chip supports several general-purpose i/o signals (gpios) that can be used on the system board. there are two classifications of gpio available: the gpiox signals, which are programmable as inputs or outputs only, and the gpio_csx signals. the gpio_csx signals have many programmable op- tions. they can be configured as chip selects. as out- puts, these signals are individually programmable to be high or low for the following pmu modes: hyper, high- speed, low-speed, standby, and suspend. as inputs, they can be programmed to cause system manage- ment interrupts (smis), non-maskable interrupts (nmis), wake-ups, or activities for the power manage- ment unit. they can also be used as i/o or memory chip selects. infrared port for wireless communication the lansc400 and lansc410 microcontrollers sup- port infrared data transfer. this support consists of adding additional transmit and receive serializers as well as a controlling state machine and dma interface to the internal uart. the integrated infrared port includes these features: n low-speed mode supports all bit rates from uart, up to 115 kbit/s n high-speed mode transfers 1.152 mbit/s using dma dual pc card controller (lansc400 microcontroller only) the pc card host bus adapter included on the lansc400 microcontroller conforms to pcmcia stan- dard release 2.1 . it provides support for two sockets, each implementing the pc card memory and i/o inter- faces. the pc card controller is not supported on the lansc410 microcontroller. the pc card controller includes the following features: n exca-compliant, 82365-register-set compatible n 8-bit and 16-bit data bus n dma transfers between i/o pc cards and system dram n ten available memory windows, five per socket of the two pc card sockets supported, only one is available in all modes of operation. the second socket is multiplexed with the parallel port and gpio features. register set compatibility with the 82365sl pc card interface controller is maintained where features are common to both controllers. of the ten memory windows available, six are dedi- cated to the pc card controller and four are shared with memory mapping system (mms) windows cCf. two of the three rom/flash memory chip selects can be remapped to a pc card socket via pinstrap or soft- ware control. this feature supports reprogramming of soldered down flash memory boot devices and also simplifies testing of bios/xip os code. graphics controller for cga-compatible text and graphics (lansc400 microcontroller only) the graphics controller included on the lansc400 mi- crocontroller offers a low-cost integrated graphics solu- tion for the mobile terminal market. integration with the main processor and system logic affords the advan-
18 lan?sc400 and lansc410 microcontrollers data sheet tages of an integrated local-bus interface and frame and font buffers that are shared with main memory. the graphics controller is not supported on the lansc410 microcontroller. the graphics controller includes the following features: n supports multiple panel resolutions n provides internal unified memory architecture (uma) with optional write-through caching of graphics buffers n stores frame and font buffer data in system dram, eliminates extra memory chip n provides software compatibility with color graphics adapter (cga), monochrome display adapter (mda), and hercules graphics adapter (hga) text and graphics n supports single-scan or dual-scan monochrome lcd panels with 4-bit or 8-bit data interface n typical panels supported include: C 640 x 200, 640 x 240, 640 x 480, 480 x 320, 480 x 240, 480 x 128, 320 x 200, 320 x 240 C other resolutions can be supported n supports single-scan color stn panels with 8-bit interface, same resolutions as monochrome mode n internal local-bus interface provides high perfor- mance n logical screen can be larger than physical window. n supports panning and scrolling n supports horizontal dot doubling and vertical line doubling the following mda/cga-compatible text mode fea- tures are supported: n 40, 64, or 80 columns with characters 16, 10, or 8 pixels wide n variable height characters up to 32 lines n variable width characters8, 10, or 16 pixels n mda monochrome, or cga 4 gray shades, 16 gray shades, or 16-colors n 16-kbyte downloadable font area, relocatable on 16-kbyte boundaries within lower 16 mbytes of system dram (can be write protected) n 16-kbyte frame buffer, relocatable on either 16-kbyte boundaries within lower 16 mbyte of system dram (cga-compatible mode) or 32-kbyte boundaries when the frame buffer is larger than 16 kbyte (flat-mapped mode) the following graphics mode features are supported: n 640 x 200 1 bit-per-pixel, cga-compatible graphics buffer memory map n 320 x 200 2 bits-per-pixel, cga-compatible graph- ics buffer memory map n 640 x 480 2 bits-per-pixel, flat memory map (lower resolutions supported) n 640 x 480 1 bit-per-pixel, flat memory map n 1, 2, or 4 bits-per-pixel packed-pixel flat-mapped graphics up to 640 x 240/480 x 320 with two map- ping modes: C 16-kbyte window with bank swapping to ad- dress up to 64 kbyte of graphics frame buffer while consuming only 16 kbyte of dos/real- mode cpu address space C direct-mapped (no bank swapping) with locat- able base address, up to 128-kbyte direct ad- dressability n hercules graphics mode emulation (hga) jtag test features the lansc400 and lansc410 microcontrollers pro- vide a boundary-scan interface based on the ieee std 1149.1, standard test access port and boundary- scan architecture . the test access port provides a scan interface for testing the microcontroller and sys- tem hardware in a production environment. it contains extensions that allow a hardware-development system to control and observe the microcontroller without inter- posing hardware between the microcontroller and the system. system interfaces data buses the lansc400 and lansc410 microcontrollers pro- vide 32 bits of data that are divided into two separate 16-bit buses. n system data bus : the system (or peripheral) data bus (sd15Csd0) is always 16 bits wide and is shared between isa, 8-bit or 16-bit rom/flash memory, and pc card peripherals (lansc400 microcontroller only). it can be directly connected to all of these devices. in addition, these signals are the upper word of the vesa local (vl) data bus, the 32-bit dram interface, and the 32-bit rom interface. n data bus : the d15Cd0 data bus is used during 16-bit dram cycles. for 32-bit dram, vl-bus, and rom cycles, this bus is combined with the system data bus. in other words, the data bus signals (d31Cd16) are shared with the system data bus signals sd15Csd0.
lan?sc400 and lansc410 microcontrollers data sheet 19 the lansc400 and lansc410 microcontrollers sup- port the data bus configurations listed below. external transceivers or buffers can be used to isolate the buses. n 16-bit dram bus, 8-/16-bit rom, 32-bit vl-bus disabled, internal graphics controller enabled/ disabled n 16-/32-bit dram bus, 8/16-bit rom, 32-bit vl-bus enabled/disabled, internal graphics controller disabled n 16-/32-bit dram bus, 32-bit rom, 32-bit vl-bus enabled/disabled, internal graphics controller disabled see figure 2 on page 22 and figure 3 on page 23 for block diagrams of example systems. the lansc400 and lansc410 microcontrollers offer flexibility in configuring the rom and dram data buses for different widths. the widths (8/16/32 bits) for romcs0 are programmed during power-up through two pinstraps, cfg0 and cfg1. the dram widths (16/32 bits) are programmed through configuration registers. up to four 16- or 32-bit banks of dram are supported. two of the three rom/flash memory chip selects (romcs2 Cromcs0 ) can be remapped to a pc card socket via pinstrap or software control. this feature supports reprogramming of soldered-down flash memory boot devices and also simplifies testing of bios/xip (execute in place) os code. address buses there are two external address buses on the lansc400 and lansc410 microcontrollers. n system address bus : the sa25Csa0 system ad- dress bus outputs the physical memory or i/o port latched addresses. these addresses are used by all external peripheral devices other than main sys- tem dram. in addition, the system address bus is the local address bus in vl-bus mode. n dram address bus : dram row and column ad- dresses are multiplexed onto the dram address bus (ma12Cma0). row addresses are driven onto this bus and are valid upon the falling edge of ras . column addresses are driven onto this bus and are valid upon the falling edge of cas . the sa bus is shared between the isa bus, the vl-bus, the rom/flash memory controller and, on the lansc400 microcontroller, the pc card controller. the lansc400 and lansc410 microcontrollers provide programmable drive strengths in the i/o buffers to accommodate loading for various system configurations. memory management the lansc400 and lansc410 microcontrollers man- age up to nine separate physical device memory ad- dress spaces. all but the isa memory address space can have a depth of up to 64 mbyte each. the isa bus memory area is limited to 16 mbyte, as defined by isa specifications. the microcontroller will drive all 26 ad- dress lines on isa cycles to allow up to 64-mbyte ad- dress space, as described in the memory management section of the lansc400 and lansc410 microcon- trollers users manual (order #21030)refer to the subsection on isa bus addressing). the nine memory spaces are: n system memory address space (dram) n rom0 memory address space (romcs0 signal) n rom1 memory address space (romcs1 signal) n rom2 memory address space (romcs2 signal) n pc card socket a memory address spaces (com- mon and attribute) (lansc400 microcontroller only) n pc card socket b memory address spaces (com- mon and attribute) (lansc400 microcontroller only) n external isa/vl-bus memory address space the system memory address space (dram) is acces- sible using direct-mapped cpu addresses and can also be accessed by the cpu in an indirect method using the memory mapping system (mms). on the lansc400 microcontroller, dram is also accessible by the integrated graphics controller if enabled. the rom0 address space is partially accessible via a direct mapping of the cpu address bus and partially accessible via the mms. the rom1 and rom2 address spaces are only accessible indirectly using the mms. on the lansc400 microcontroller, the pc card ad- dress spaces are accessed through a separate, 82365sl-compatible address mapping system. the isa/vl-bus address space is accessible as a direct mapping of the cpu address bus. isa memory cycles are generated when the cpu generates a memory cycle that is not detected as an access to any other memory space. an isa bus memory cycle can also be generated if the cpu generates a memory address that resides in the isa overlapping memory region window. this window can be defined to overlay any system memory region below 16 mbyte.
20 lan?sc400 and lansc410 microcontrollers data sheet isa bus interface for external isa peripherals the isa interface consists of a subset of isa-compati- ble bus signals, allowing for the connection of 8- or 16-bit devices supporting isa-compatible i/o, memory, and dma cycles. the following features are supported: n 8.2944-mhz maximum bus clock speed n programmable dma clock speed up to 16 mhz n 8-bit and 16-bit isa i/o and memory cycles (isa memory is non-cacheable) n direct connection to 3- or 5-volt peripherals eight programmable irq input signals are available. these interrupts can be routed via software to any available pc/at-compatible interrupt channel. two programmable dma channels are available for ex- ternal dma peripherals. these dma channels can be routed to software to any available isa dma channel. vesa local (vl) bus interface supports 32-bit memory and i/o targets the vesa local (vl) bus controller provides the sig- nals and associated timing necessary to support a sin- gle vesa compliant vl-bus target. multiple vl-bus targets can be supported using external circuitry to allow multiple vl devices to share the vl_ldev sig- nal. this allows the lansc400 and lansc410 micro- controllers to operate as a normal vl-bus motherboard controller, in accordance with the vl-bus standard 2.0 . on the lansc400 microcontroller, the vl-bus is available only when the internal graphics controller is disabled. the microcontrollers vl-bus controller includes the following features: n 33-mhz operation at 3.3 v n 32-bit data bus n burst-mode transfers n register control of local bus reset vesa bus mastering and dma transfers to and from the vl-bus target are not supported. vl memory is non-cacheable. system considerations figure 1 shows the lansc400 microcontroller as it might be used in a minimal system design. figure 2 and figure 3 show more complex system de- signs for each microcontroller and the features that are traded for others because of pin multiplexing. n the lansc400 and lansc410 microcontrollers support a maximum of 4 banks of 32-bit dram, but because the ras and cas signals for the high word and for banks 2 and 3 are traded for keyboard row signals, the minimum system would have one or two banks of dram (either bank 0 or bank 1) populated with 16-bit drams. the ma12 signal for asymmetrical support is also traded with a keyboard row signal. n because the vl-bus and the graphics controller share control signals on the lansc400 microcon- troller, use of the internal graphics controller is traded with having an external vl-bus on that mi- crocontroller. n if either 32-bit drams, 32-bit roms, or the vl-bus is enabled, the internal graphics controller on the lansc400 microcontroller is unavailable because of internal design constraints. n the lansc400 and lansc410 microcontrollers provide an absolute minimum of dedicated isa con- trol signals. any additional isa controls are traded with gpios or keyboard rows and columns. n the sd buffer shares control signals with some of the gpios. this buffer controls the high word of the d data bus (d31Cd16). note that using the sd buffer is optional. the high word of the d data bus can be hooked up directly to devices that want the sd data bus (sd15Csd0). buffering aids in voltage translation or isolation for heavy loading. n the r32bfoe signal buffers the high word of the d data bus (d31Cd16) for 32-bit roms. the control signal associated with the rom32 buffer is shared with a keyboard row. n on the lansc400 microcontroller, the parallel port is traded for pc card socket b. it requires an exter- nal buffer and latch. n the serial and infrared ports share the same inter- nal uart. real-time switching between the two is supported; however, only one port is available at any given time. n romcs2 is not connected to a dedicated pin. soft- ware can enable and map it to any of the 15 gpio_cs signals.
lan?sc400 and lansc410 microcontrollers data sheet 21 figure 1. typical mobile terminal design column conn pc card socket a pc card socket b lcd serial conn infrared matrix power supply backup 32-khz crystal ctrl sa25 Csa0 lcd serial infrared columns rows pc card b ctrl pc card a ctrl ctrl sd15Csd0 gpio_cs12Cgpio_cs0 sd15Csd0 ctrl ctrl ctrl sa sa loop filters high d bank 0 bank 1 ma d ctrl low low word sd sd ma11Cma0 ctrl d15Cd0 keyboard row conn pwr conn bios/os flash/ rom sa25Csa1 ctrl battery speaker battery lansc400 microcontroller dram dram serial translator
22 lan?sc400 and lansc410 microcontrollers data sheet figure 2. system diagram with trade-offslansc400 microcontroller pc card socket a pc card socket b lcd conn serial translator serial conn infrared keyboard power supply battery 32-khz crystal ctrl sa lcd serial infrared columns rows pc card b ctrl pc card a ctrl ctrl parallel port connector buffer latch vl bus device sd buffer ctrl sd sd sa sd sa high d sa a dashed box indicates a feature that is optional or is traded for another. isa bus device ctrl ctrl ctrl sd ctrl ctrl ctrl ctrl sa sa loop filters high d bank 0 bank 1 ma d ctrl dram bank 2 dram bank 3 dram ctrl ma12 dram dram dram low dram dram low d high word low word sd sd ctrl ctrl rom32 buffer notes: low d lansc400 microcontroller backup battery bios/ os/ apps flash rom
lan?sc400 and lansc410 microcontrollers data sheet 23 figure 3. system design with trade-offslansc410 microcontroller serial translator serial conn infrared keyboard power supply 32-khz crystal ctrl sa serial irda columns rows parallel ctrl rom ctrl parallel port connector buffer and latch vl bus device sd buffer ctrl sd sd sa sa high d sa a dashed box indicates a feature that is optional or is traded for another. isa bus device isa ctrl ctrl ctrl sd ctrl ctrl loop filters high d bank 0 bank 1 ma d ctrl dram bank 2 dram bank 3 dram ma12 dram dram dram low dram dram low d high word low word ctrl ctrl rom32 buffer notes: low d lansc410 microcontroller backup battery ctrl dram vl-bus ctrl bios/ os/ apps flash rom
24 lan?sc400 and lansc410 microcontrollers data sheet connection diagramlansc400 and lansc410 microcontrollers 292 ball grid array (bga) package top view (from component side looking through to bottom) a b c d e f g h j k l m n p r t u v w y a b c d e f g h j k l m n p r t u v w y 20 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
lan?sc400 and lansc410 microcontrollers data sheet 25 pin designations this section identifies the pins of the lansc400 and lansc410 microcontrollers and lists the signals asso- ciated with each pin. several different tables are included in this section. n the pin designations (pin number)lansc400 microcontroller table beginning on page 26 lists the lansc400 microcontroller signals sorted by pin number. the pin designations (pin number)lansc410 microcontroller table on page 33 lists the lansc410 microcontroller signals sorted by pin number. along with the connection diagram on page 24, these tables can be used to associate the complete pin name (including all multiplexed functions) with the physical pin on the bga package. n the pin designations (pin name)lansc400 microcontroller table on page 29 lists the lansc400 microcontroller signals sorted in alphabetical order. the pin designations (pin name)lansc410 microcontroller table on page 36 lists the lansc410 microcontroller signals sorted in alphabetical order. all multiplexed signals are included in these lists. note that these tables should not be used to determine primary and secondary functions for multiplexed pins because the ordering was changed to alphabetize every function. please refer to the pin designations (pin number) table or the pin state tables for the definitive listing of primary and secondary functions in the correct order for each pin. n the pin state tables beginning on page 42, which group pins alphabetically by function, show pin states during reset, normal operation, and suspend mode, along with output drive strength, maximum load, supply source, and power-down groups. n the signal description table beginning on page 62 includes complete pin descriptions in alphabetical order by function. n the table beginning on page 70 clarifies the configuration options for those pins having multiple functions. pin naming the signal name column in the pin designation tables beginning on page 26 and in the pin state tables be- ginning on page 40 is decoded as follows: name1/name2 {name3} [name4] [[name5]] name1 this is the only function for the pin. name1/name2 the slash separates two functions that are available on the pin at the same time (i.e., at different times in the same design the pin is used for different functions). {name3} the name in braces is the pin function during a hard- ware reset. [name4] the name in square brackets is the alternative function for the pin, selected by firmware configuration. only one function is available for each configuration. [[name5]] the name inside double square brackets is the alternate function for the pin, selected by a hardware configuration pin state at power-on reset. this does not apply to [[bndscn_tck]], [[bndscn_tms]], [[bndscn_tdi]], and [[bndscn_tdo]]. these four alternate functions are enabled by the bndscn_en signal. only one function is available for each configuration. pin changes for the lansc410 microcontroller the following signals supported on the lansc400 microcontroller are not available on the lansc410 microcontroller. n configuration signal: cfg2 n pc card controller signals: mcel_a , mcel_b , mceh_a , mceh_b , rst_a, rst_b, reg_a , reg_b , cd_a , cd_b , cd_a2 , rdy_a , rdy_b , bvd1_a, bvd1_b, bvd2_a, bvd2_b, wp_a, wp_b, wait_ab , oe , we , icdir, pcma_v cc , pcma_vpp1, pcma_vpp2, pcmb_v cc , pcmb_vpp1, pcmb_vpp2 n graphics controller signals: lcdd7Clcdd0, m, lc, sck, frm, lvee , lvdd n loop filter signal: lf_vid
26 lan?sc400 and lansc410 microcontrollers data sheet pin designations ( pin number)lansc400 microcontroller pin no. signal name pin no. signal name pin no. signal name a1 kbd_col5/pirq6 b19 kbd_row0 [casl2] d17 gpio_cs3 [[dbufrdh ]] a2 kbd_col2/pirq3 b20 lcdd0 [vl_rst ] d18 lcdd2 [vl_w/r ] a3 kbd_row13 [[r32bfoe ]] c1 kbd_row11 [sbhe ] d19 lcdd4 [vl_lrdy ] a4 d15 c2 kbd_row8 [pdrq1] d20 lcdd7 [vl_be3 ] a5 d12 c3 kbd_col4/pirq5 e1 v cc a6 d9 c4 gpio_cs4 [[dbufoe ]] e2 kbd_col0 [xt_data] a7 d7 c5 kbd_col7 e3 kbd_row9 [pirq2] a8 v cc c6 d13 e4 gnd a9 d4 c7 d10 e17 v cc a10 d1 c8 d6 e18 lcdd5 [vl_d/c ] a11 mwe c9 d2 e19 frm [vl_lclk] a12 ma2 {cfg2} c10 ma0 {cfg0} e20 lc [vl_be1 ] a13 v cc c11 ma4 f1 sd4 [d20] a14 ma5 c12 ma7 f2 sd1 [d17] a15 ma8 c13 ma10 f3 kbd_row12 [mcs16 ] a16 ma11 c14 casl1 f4 gnd a17 cash1 c15 ras0 f17 lcdd6 [vl_ldev ] a18 v cc c16 kbd_row5 [ras3 ] f18 m [vl_be2 ] a19 lvdd [vl_blast ] c17 kbd_row2 [cash2 ] f19 sck [vl_be0 ] a20 lvee [vl_brdy ] c18 gpio_cs2 [[dbufrdl ]] f20 sa24 b1 v cc c19 lcdd1 [vl_ads ] g1 sd6 [d22] b2 kbd_col6/pirq7 c20 lcdd3 [vl_m/io ] g2 sd3 [d19] b3 kbd_col3/pirq4 d1 kbd_col1 [xt_clk] g3 sd0 [d16] b4 v cc d2 kbd_row10 [bale] g4 gnd b5 d14 d3 kbd_row7 [pdack1 ] g17 v cc b6 d11 d4 gnd g18 gpio20 [cd_a2 ] b7 d8 d5 gnd g19 sa22 b8 d5 d6 gnd g20 sa21 b9 d3 d7 gnd h1 v cc b10 d0 d8 gnd h2 sd5 [d21] b11 ma1 {cfg1} d9 gnd h3 sd2 [d18] b12 ma3 {cfg3} d10 gnd h4 gnd b13 ma6 d11 gnd h8 gnd b14 ma9 d12 gnd h9 gnd b15 casl0 d13 cash0 h10 gnd b16 v cc d14 ras1 h11 gnd b17 kbd_row6 [ma12] d15 kbd_row4 [ras2 ] h12 gnd b18 kbd_row3 [cash3 ] d16 kbd_row1 [casl3 ] h13 gnd
lan?sc400 and lansc410 microcontrollers data sheet 27 pin designations ( pin number)lansc400 microcontroller (continued) pin no. signal name pin no. signal name pin no. signal name h17 sa25 l10 gnd p3 rdy_a h18 sa23 l11 gnd p4 v cc _cpu h19 sa20 l12 gnd p17 v cc h20 sa18 l13 gnd p18 v cc j1 sd10 [d26] l17 v cc p19 sa1 j2 sd7 [d23] l18 sa10 p20 sa4 j3 v cc l19 sa9 r1 rst_a [[bndscn_tdi]] j4 gnd l20 sa11 r2 cd_a j8 gnd m1 v cc r3 bvd2_a j9 gnd m2 reg_a [[bdnscn_tdo]] r4 v cc _cpu j10 gnd m3 icdir r17 gnd j11 gnd m4 v cc _cpu r18 romcs0 j12 gnd m8 gnd r19 iow j13 gnd m9 gnd r20 sa2 j17 v cc m10 gnd t1 v cc j18 sa19 m11 gnd t2 wp_a j19 sa17 m12 gnd t3 gpio22 [ppoen ] j20 sa14 m13 gnd t4 v cc _cpu k1 sd11 [d27] m17 v cc t17 gnd k2 sd9 [d25] m18 sa7 t18 memw k3 sd8 [d24] m19 v cc t19 romcs1 k4 v cc _cpu m20 sa8 t20 sa0 k8 gnd n1 sd14 [d30] u1 wait_ab k9 gnd n2 we u2 gpio25 [ack ] [bvd1_b] k10 gnd n3 mceh_a [[bndscn_tms]] u3 gpio24 [busy] [bvd2_b] k11 gnd n4 v cc _cpu u4 gpio23 [slct] [wp_b] k12 gnd n8 gnd u5 gnd k13 gnd n9 gnd u6 gnd k17 sa16 n10 gnd u7 gnd k18 sa15 n11 gnd u8 gnd k19 sa13 n12 gnd u9 gnd k20 sa12 n13 gnd u10 gnd l1 sd12 [d28] n17 v cc u11 gnd l2 sd13 [d29] n18 sa3 u12 gnd l3 sd15 [d31] n19 sa5 u13 gnd l4 v cc _cpu n20 sa6 u14 gnd l8 gnd p1 oe u15 gnd l9 gnd p2 mcel_a [[bndscn_tck]] u16 gnd
28 lan?sc400 and lansc410 microcontrollers data sheet pin designations ( pin number)lansc400 microcontroller (continued) pin no. signal name pin no. signal name pin no. signal name u17 gnd v19 gpio_cs0 y1 v cc u18 v cc v20 romrd y2 gpio28 [init ] [reg_b ] u19 romwr w1 gpio30 [afdt ] [mceh_b ] y3 lf_int u20 ior w2 gpio26 [pe] [rdy_b ] y4 32kxtal2 v1 bvd1_a w3 gpio29 [slctin ] [rst_b] y5 gnd_analog v2 gpio31 [strb ] [mcel_b ] w4 lf_ls y6 32kxtal1 v3 gpio21 [ppdwe ] w5 lf_vid y7 reset v4 gpio27 [error ] [cd_b ] w6 v cc _a y8 dtr v5 lf_hs w7 v cc _rtc y9 sirin v6 bbatsen w8 rts y10 sout v7 spkr w9 v cc y11 bndscn_en v8 sirout w10 dsr y12 sus_res/kbd_row14 v9 dcd w11 sin y13 bl1 v10 cts w12 acin y14 gpio18 [pcmb_vpp2] v11 rin w13 bl2 y15 gpio15 [pcma_vpp2] v12 rstdrv w14 bl0 [clk_io] y16 v cc v13 v cc w15 gpio17 [pcmb_vpp1] y17 gpio_cs12 [pdrq0] v14 gpio19 [lbl2 ] w16 gpio_cs14 [pcma_vpp1] y18 gpio_cs9 [tc] v15 gpio16 [pcmb_v cc ] w17 gpio_cs11 [pdack0 ] y19 gpio_cs7 [pirq1] v16 gpio_cs13 [pcma_v cc ] w18 gpio_cs8 [pirq0] y20 gpio_cs1 v17 gpio_cs10 [aen] w19 gpio_cs5 [iocs16 ] v18 gpio_cs6 [iochrdy] w20 memr
lan?sc400 and lansc410 microcontrollers data sheet 29 pin designations ( pin name)lansc400 microcontroller signal name pin no. signal name pin no. signal name pin no. acin w12 d2 c9 gnd d4 [ack ] [bvd1_b] gpio25 u2 d3 b9 gnd d5 [aen] gpio_cs10 v17 d4 a9 gnd d6 [afdt ] [mceh_b ] gpio30 w1 d5 b8 gnd d7 [bale] kbd_row10 d2 d6 c8 gnd d8 bbatsen v6 d7 a7 gnd d9 bl0 [clk_io] w14 d8 b7 gnd d10 bl1 y13 d9 a6 gnd d11 bl2 w13 d10 c7 gnd d12 bndscn_en y11 d11 b6 gnd e4 [[bndscn_tck]] mcel_a p2 d12 a5 gnd f4 [[bndscn_tdi]] rst_a r1 d13 c6 gnd g4 [[bndscn_tdo]] reg_a m2 d14 b5 gnd h4 [[bndscn_tms]] mceh_a n3 d15 a4 gnd h8 [busy] [bvd2_b] gpio24 u3 [d16] sd0 g3 gnd h9 bvd1_a v1 [d17] sd1 f2 gnd h10 [bvd1_b] gpio25 [ack ] u2 [d18] sd2 h3 gnd h11 bvd2_a r3 [d19] sd3 g2 gnd h12 [bvd2_b] gpio24 [busy] u3 [d20] sd4 f1 gnd h13 cash0 d13 [d21] sd5 h2 gnd j4 cash1 a17 [d22] sd6 g1 gnd j8 [cash2 ] kbd_row2 c17 [d23] sd7 j2 gnd j9 [cash3 ] kbd_row3 b18 [d24] sd8 k3 gnd j10 casl0 b15 [d25] sd9 k2 gnd j11 casl1 c14 [d26] sd10 j1 gnd j12 [casl2 ] kbd_row0 b19 [d27] sd11 k1 gnd j13 [casl3 ] kbd_row1 d16 [d28] sd12 l1 gnd k8 cd_a r2 [d29] sd13 l2 gnd k9 [cd_a2 ] gpio20 g18 [d30] sd14 n1 gnd k10 [cd_b ] gpio27 [error ] v4 [d31] sd15 l3 gnd k11 {cfg0} ma0 c10 [[dbufoe ]] gpio_cs4 c4 gnd k12 {cfg1} ma1 b11 [[dbufrdh ]] gpio_cs3 d17 gnd k13 {cfg2} ma2 a12 [[dbufrdl ]] gpio_cs2 c18 gnd l8 {cfg3} ma3 b12 dcd v9 gnd l9 [clk_io] bl0 w14 dsr w10 gnd l10 cts v10 dtr y8 gnd l11 d0 b10 [error ] [cd_b ] gpio27 v4 gnd l12 d1 a10 frm [vl_lclk] e19 gnd l13
30 lan?sc400 and lansc410 microcontrollers data sheet pin designations ( pin name)lansc400 microcontroller (continued) signal name pin no. signal name pin no. signal name pin no. gnd m8 gpio_cs10 [aen] v17 kbd_row0 [casl2 ] b19 gnd m9 gpio_cs11 [pdack0 ] w17 kbd_row1 [casl3 ] d16 gnd m10 gpio_cs12 [pdrq0] y17 kbd_row2 [cash2 ] c17 gnd m11 gpio_cs13 [pcma_v cc ] v16 kbd_row3 [cash3 ] b18 gnd m12 gpio_cs14 [pcma_vpp1] w16 kbd_row4 [ras2 ] d15 gnd m13 gpio15 [pcma_vpp2] y15 kbd_row5 [ras3 ] c16 gnd n8 gpio16 [pcmb_vcc ] v15 kbd_row6 [ma12] b17 gnd n9 gpio17 [pcmb_vpp1] w15 kbd_row7 [pdack1 ] d3 gnd n10 gpio18 [pcmb_vpp2] y14 kbd_row8 [pdrq1] c2 gnd n11 gpio19 [lbl2 ] v14 kbd_row9 [pirq2] e3 gnd n12 gpio20 [cd_a2 ] g18 kbd_row10 [bale] d2 gnd n13 gpio21 [ppdwe ] v3 kbd_row11 [sbhe ] c1 gnd r17 gpio22 [ppoen ] t3 kbd_row12 [mcs16 ] f3 gnd t17 gpio23 [slct] [wp_b] u4 kbd_row13 [[r32bfoe ]] a3 gnd u5 gpio24 [busy] [bvd2_b] u3 kbd_row14 / sus_res y12 gnd u6 gpio25 [ack ] [bvd1_b] u2 [lbl2 ] gpio19 v14 gnd u7 gpio26 [pe] [rdy_b ] w2 lc [vl_be1 ] e20 gnd u8 gpio27 [error ] [cd_b ] v4 lcdd0 [vl_rst ] b20 gnd u9 gpio28 [init ] [reg_b ] y2 lcdd1 [vl_ads ] c19 gnd u10 gpio29 [slctin ] [rst_b] w3 lcdd2 [vl_w/r ] d18 gnd u11 gpio30 [afdt ] [mceh_b ] w1 lcdd3 [vl_m/io ] c20 gnd u12 gpio31 [strb ] [mcel_b ] v2 lcdd4 [vl_lrdy ] d19 gnd u13 icdir m3 lcdd5 [vl_d/c ] e18 gnd u14 [init ] [reg_b ] gpio28 y2 lcdd6 [vl_ldev ] f17 gnd u15 [iochrdy] gpio_cs6 v18 lcdd7 [vl_be3 ] d20 gnd u16 [iocs16 ] gpio_cs5 w19 lf_hs v5 gnd u17 ior u20 lf_int y3 gnd_analog y5 iow r19 lf_ls w4 gpio_cs0 v19 32kxtal1 y6 lf_vid w5 gpio_cs1 y20 32kxtal2 y4 lvdd [vl_blast ] a19 gpio_cs2 [[dbufrdl ]] c18 kbd_col0 [xt_data] e2 lvee [vl_brdy ] a20 gpio_cs3 [[dbufrdh ]] d17 kbd_col1 [xt_clk] d1 m [vl_be2 ] f18 gpio_cs4 [[dbufoe ]] c4 kbd_col2/pirq3 a2 ma0 {cfg0} c10 gpio_cs5 [iocs16 ] w19 kbd_col3/pirq4 b3 ma1 {cfg1} b11 gpio_cs6 [iochrdy] v18 kbd_col4/pirq5 c3 ma2 {cfg2} a12 gpio_cs7 [pirq1] y19 kbd_col5/pirq6 a1 ma3 {cfg3} b12 gpio_cs8 [pirq0] w18 kbd_col6/pirq7 b2 ma4 c11 gpio_cs9 [tc] y18 kbd_col7 c5 ma5 a14
lan?sc400 and lansc410 microcontrollers data sheet 31 pin designations ( pin name)lansc400 microcontroller (continued) signal name pin no. signal name pin no. signal name pin no. ma6 b13 ras0 c15 sa20 h19 ma7 c12 ras1 d14 sa21 g20 ma8 a15 [ras2 ] kbd_row4 d15 sa22 g19 ma9 b14 [ras3 ] kbd_row5 c16 sa23 h18 ma10 c13 rdy_a p3 sa24 f20 ma11 a16 [rdy_b ] gpio26 [pe] w2 sa25 h17 [ma12] kbd_row6 b17 reg_a [[bndscn_tdo]] m2 [sbhe ] kbd_row11 c1 mceh_a [[bndscn_tms]] n3 [r eg_b ] gpio28 [init ] y2 sck [vl_be0 ] f19 [mceh_b ] gpio30 [afdt ] w1 reset y7 sd0 [d16] g3 mcel_a [[bndscn_tck]] p2 rin v11 sd1 [d17] f2 [mcel_b ] gpio31 [strb ] v2 romcs0 r18 sd2 [d18] h3 [mcs16 ] kbd_row12 f3 romcs1 t19 sd3 [d19] g2 memr w20 romrd v20 sd4 [d20] f1 memw t18 romwr u19 sd5 [d21] h2 mwe a11 rst_a [[bndscn_tdi]] r1 sd6 [d22] g1 oe p1 [rst_b] gpio29 [slctin ] w3 sd7 [d23] j2 [pcma_v cc ] gpio_cs13 v16 rstdrv v12 sd8 [d24] k3 [pcma_vpp1] gpio_cs14 w16 rts w8 sd9 [d25] k2 [pcma_vpp2] gpio15 y15 sa0 t20 sd10 [d26] j1 [pcmb_v cc ] gpio16 v15 sa1 p19 sd11 [d27] k1 [pcmb_vpp1] gpio17 w15 sa2 r20 sd12 [d28] l1 [pcmb_vpp2] gpio18 y14 sa3 n18 sd13 [d29] l2 [pdack0 ] gpio_cs11 w17 sa4 p20 sd14 [d30] n1 [pdack1 ] kbd_row7 d3 sa5 n19 sd15 [d31] l3 [pdrq0] gpio_cs12 y17 sa6 n20 sin w11 [pdrq1] kbd_row8 c2 sa7 m18 sirin y9 [pe] [rdy_b ] gpio26 w2 sa8 m20 sirout v8 [pirq0] gpio_cs8 w18 sa9 l19 [slct] [wp_b] gpio23 u4 [pirq1] gpio_cs7 y19 sa10 l18 [slctin ] [rst_b] gpio29 w3 [pirq2] kbd_row9 e3 sa11 l20 sout y10 pirq3/kbd_col2 a2 sa12 k20 spkr v7 pirq4/kbd_col3 b3 sa13 k19 [strb ] [mcel_b ] gpio31 v2 pirq5/kbd_col4 c3 sa14 j20 sus_res/kbd_row14 y12 pirq6/kbd_col5 a1 sa15 k18 [tc] gpio_cs9 y18 pirq7/kbd_col6 b2 sa16 k17 v cc a8 [ppdwe ] gpio21 v3 sa17 j19 v cc a13 [ppoen ] gpio22 t3 sa18 h20 v cc a18 [[r32bfoe ]] kbd_row13 a3 sa19 j18 v cc b1
32 lan?sc400 and lansc410 microcontrollers data sheet pin designations ( pin name)lansc400 microcontroller (continued) signal name pin no. signal name pin no. signal name pin no. v cc b4 v cc v13 [vl_be3 ] lcdd7 d20 v cc b16 v cc w9 [vl_blast ] lvdd a19 v cc e1 v cc y1 [vl_brdy ] lvee a20 v cc e17 v cc y16 [vl_d/c ] lcdd5 e18 v cc g17 v cc _a w6 [vl_lclk] frm e19 v cc h1 v cc _cpu k4 [vl_ldev ] lcdd6 f17 v cc j3 v cc _cpu l4 [vl_lrdy ] lcdd4 d19 v cc j17 v cc _cpu m4 [vl_m/io ] lcdd3 c20 v cc l17 v cc _cpu n4 [vl_rst ] lcdd0 b20 v cc m1 v cc _cpu p4 [vl_w/r ] lcdd2 d18 v cc m17 v cc _cpu r4 wait_ab u1 v cc m19 v cc _cpu t4 we n2 v cc n17 v cc _rtc w7 wp_a t2 v cc p17 [vl_ads ] lcdd1 c19 [wp_b] gpio23 [slct] u4 v cc p18 [vl_be0 ] sck f19 [xt_clk] kbd_col1 d1 v cc t1 [vl_be1 ] lc e20 [xt_data] kbd_col0 e2 v cc u18 [vl_be2 ] m f18
lan?sc400 and lansc410 microcontrollers data sheet 33 pin designations ( pin number)lansc410 microcontroller pin no. signal name pin no. signal name pin no. signal name a1 kbd_col5/pirq6 b19 kbd_row0 [casl2] d17 gpio_cs3 [[dbufrdh ]] a2 kbd_col2/pirq3 b20 vl_rst d18 vl_w/r a3 kbd_row13 [[r32bfoe ]] c1 kbd_row11 [sbhe ] d19 vl_lrdy a4 d15 c2 kbd_row8 [pdrq1] d20 vl_be3 a5 d12 c3 kbd_col4/pirq5 e1 v cc a6 d9 c4 gpio_cs4 [[dbufoe ]] e2 kbd_col0 [xt_data] a7 d7 c5 kbd_col7 e3 kbd_row9 [pirq2] a8 v cc c6 d13 e4 gnd a9 d4 c7 d10 e17 v cc a10 d1 c8 d6 e18 vl_d/c a11 mwe c9 d2 e19 vl_lclk a12 ma2 c10 ma0 {cfg0} e20 vl_be1 a13 v cc c11 ma4 f1 sd4 [d20] a14 ma5 c12 ma7 f2 sd1 [d17] a15 ma8 c13 ma10 f3 kbd_row12 [mcs16 ] a16 ma11 c14 casl1 f4 gnd a17 cash1 c15 ras0 f17 vl_ldev a18 v cc c16 kbd_row5 [ras3 ] f18 vl_be2 a19 vl_blast c17 kbd_row2 [cash2 ] f19 vl_be0 a20 vl_brdy c18 gpio_cs2 [[dbufrdl ]] f20 sa24 b1 v cc c19 vl_ads g1 sd6 [d22] b2 kbd_col6/pirq7 c20 vl_m/io g2 sd3 [d19] b3 kbd_col3/pirq4 d1 kbd_col1 [xt_clk] g3 sd0 [d16] b4 v cc d2 kbd_row10 [bale] g4 gnd b5 d14 d3 kbd_row7 [pdack1 ] g17 v cc b6 d11 d4 gnd g18 gpio20 b7 d8 d5 gnd g19 sa22 b8 d5 d6 gnd g20 sa21 b9 d3 d7 gnd h1 v cc b10 d0 d8 gnd h2 sd5 [d21] b11 ma1 {cfg1} d9 gnd h3 sd2 [d18] b12 ma3 {cfg3} d10 gnd h4 gnd b13 ma6 d11 gnd h8 gnd b14 ma9 d12 gnd h9 gnd b15 casl0 d13 cash0 h10 gnd b16 v cc d14 ras1 h11 gnd b17 kbd_row6 [ma12] d15 kbd_row4 [ras2 ] h12 gnd b18 kbd_row3 [cash3 ] d16 kbd_row1 [casl3 ] h13 gnd
34 lan?sc400 and lansc410 microcontrollers data sheet pin designations ( pin number)lansc410 microcontroller (continued) pin no. signal name pin no. signal name pin no. signal name h17 sa25 l10 gnd p3 reserved h18 sa23 l11 gnd p4 v cc _cpu h19 sa20 l12 gnd p17 v cc h20 sa18 l13 gnd p18 v cc j1 sd10 [d26] l17 v cc p19 sa1 j2 sd7 [d23] l18 sa10 p20 sa4 j3 v cc l19 sa9 r1 [[bndscn_tdi]] j4 gnd l20 sa11 r2 reserved j8 gnd m1 v cc r3 reserved j9 gnd m2 [[bndscn_tdo]] r4 v cc _cpu j10 gnd m3 reserved r17 gnd j11 gnd m4 v cc _cpu r18 romcs0 j12 gnd m8 gnd r19 iow j13 gnd m9 gnd r20 sa2 j17 v cc m10 gnd t1 v cc j18 sa19 m11 gnd t2 reserved j19 sa17 m12 gnd t3 gpio22 [ppoen ] j20 sa14 m13 gnd t4 v cc _cpu k1 sd11 [d27] m17 v cc t17 gnd k2 sd9 [d25] m18 sa7 t18 memw k3 sd8 [d24] m19 v cc t19 romcs1 k4 v cc _cpu m20 sa8 t20 sa0 k8 gnd n1 sd14 [d30] u1 reserved k9 gnd n2 reserved u2 gpio25 [ack ] k10 gnd n3 [[bndscn_tms]] u3 gpio24 [busy] k11 gnd n4 v cc _cpu u4 gpio23 [slct] k12 gnd n8 gnd u5 gnd k13 gnd n9 gnd u6 gnd k17 sa16 n10 gnd u7 gnd k18 sa15 n11 gnd u8 gnd k19 sa13 n12 gnd u9 gnd k20 sa12 n13 gnd u10 gnd l1 sd12 [d28] n17 v cc u11 gnd l2 sd13 [d29] n18 sa3 u12 gnd l3 sd15 [d31] n19 sa5 u13 gnd l4 v cc _cpu n20 sa6 u14 gnd l8 gnd p1 reserved u15 gnd l9 gnd p2 [[bndscn_tck]] u16 gnd
lan?sc400 and lansc410 microcontrollers data sheet 35 pin designations ( pin number)lansc410 microcontroller (continued) pin no. signal name pin no. signal name pin no. signal name u17 gnd v19 gpio_cs0 y1 v cc u18 v cc v20 romrd y2 gpio28 [init ] u19 romwr w1 gpio30 [afdt ] y3 lf_int u20 ior w2 gpio26 [pe] y4 32kxtal2 v1 reserved w3 gpio29 [slctin ] y5 gnd_analog v2 gpio31 [strb ] w4 lf_ls y6 32kxtal1 v3 gpio21 [ppdwe ] w5 reserved y7 reset v4 gpio27 [error ] w6 v cc _a y8 dtr v5 lf_hs w7 v cc _rtc y9 sirin v6 bbatsen w8 rts y10 sout v7 spkr w9 v cc y11 bndscn_en v8 sirout w10 dsr y12 sus_res/kbd_row14 v9 dcd w11 sin y13 bl1 v10 cts w12 acin y14 gpio18 v11 rin w13 bl2 y15 gpio15 v12 rstdrv w14 bl0 [clk_io] y16 v cc v13 v cc w15 gpio17 y17 gpio_cs12 [pdrq0] v14 gpio19 [lbl2 ] w16 gpio_cs14 y18 gpio_cs9 [tc] v15 gpio16 w17 gpio_cs11 [pdack0 ] y19 gpio_cs7 [pirq1] v16 gpio_cs13 w18 gpio_cs8 [pirq0] y20 gpio_cs1 v17 gpio_cs10 [aen] w19 gpio_cs5 [iocs16 ] v18 gpio_cs6 [iochrdy] w20 memr
36 lan?sc400 and lansc410 microcontrollers data sheet pin designations ( pin name)lansc410 microcontroller signal name pin no. signal name pin no. signal name pin no. acin w12 d10 c7 gnd e4 [ack ] gpio25 u2 d11 b6 gnd f4 [aen] gpio_cs10 v17 d12 a5 gnd g4 [afdt ] gpio30 w1 d13 c6 gnd h4 [bale] kbd_row10 d2 d14 b5 gnd h8 bbatsen v6 d15 a4 gnd h9 bl0 [clk_io] w14 [d16] sd0 g3 gnd h10 bl1 y13 [d17] sd1 f2 gnd h11 bl2 w13 [d18] sd2 h3 gnd h12 bndscn_en y11 [d19] sd3 g2 gnd h13 [[bndscn_tck]] p2 [d20] sd4 f1 gnd j4 [[bndscn_tdi]] r1 [d21] sd5 h2 gnd j8 [[bndscn_tdo]] m2 [d22] sd6 g1 gnd j9 [[bndscn_tms]] n3 [d23] sd7 j2 gnd j10 [busy] gpio24 u3 [d24] sd8 k3 gnd j11 cash0 d13 [d25] sd9 k2 gnd j12 cash1 a17 [d26] sd10 j1 gnd j13 [cash2 ] kbd_row2 c17 [d27] sd11 k1 gnd k8 [cash3 ] kbd_row3 b18 [d28] sd12 l1 gnd k9 casl0 b15 [d29] sd13 l2 gnd k10 casl1 c14 [d30] sd14 n1 gnd k11 [casl2 ] kbd_row0 b19 [d31] sd15 l3 gnd k12 [casl3 ] kbd_row1 d16 [[dbufoe ]] gpio_cs4 c4 gnd k13 {cfg0} ma0 c10 [[dbufrdh ]] gpio_cs3 d17 gnd l8 {cfg1} ma1 b11 [[dbufrdl ]] gpio_cs2 c18 gnd l9 {cfg3} ma3 b12 dcd v9 gnd l10 [clk_io] bl0 w14 dsr w10 gnd l11 cts v10 dtr y8 gnd l12 d0 b10 [error ] gpio27 v4 gnd l13 d1 a10 gnd d4 gnd m8 d2 c9 gnd d5 gnd m9 d3 b9 gnd d6 gnd m10 d4 a9 gnd d7 gnd m11 d5 b8 gnd d8 gnd m12 d6 c8 gnd d9 gnd m13 d7 a7 gnd d10 gnd n8 d8 b7 gnd d11 gnd n9 d9 a6 gnd d12 gnd n10
lan?sc400 and lansc410 microcontrollers data sheet 37 pin designations ( pin name)lansc410 microcontroller (continued) signal name pin no. signal name pin no. signal name pin no. gnd n11 gpio19 [lbl2 ] v14 kbd_row10 [bale] d2 gnd n12 gpio20 g18 kbd_row11 [sb he ] c1 gnd n13 gpio21 [ppdwe ] v3 kbd_row12 [mcs16 ] f3 gnd r17 gpio22 [ppoen ] t3 kbd_row13 [[r32bfoe ]] a3 gnd t17 gpio23 [slct] u4 kbd_row14 / sus_res y12 gnd u5 gpio24 [busy] u3 [lbl2 ] gpio19 v14 gnd u6 gpio25 [ack ] u2 lf_hs v5 gnd u7 gpio26 [pe] w2 lf_int y3 gnd u8 gpio27 [error ] v4 lf_ls w4 gnd u9 gpio28 [init ] y2 ma0 {cfg0} c10 gnd u10 gpio29 [slctin ] w3 ma1 {cfg1} b11 gnd u11 gpio30 [afdt ] w1 ma2 a12 gnd u12 gpio31 [strb ] v2 ma3 {cfg3} b12 gnd u13 [init ] gpio28 y2 ma4 c11 gnd u14 [iochrdy] gpio_cs6 v18 ma5 a14 gnd u15 [iocs16 ] gpio_cs5 w19 ma6 b13 gnd u16 ior u20 ma7 c12 gnd u17 iow r19 ma8 a15 gnd_analog y5 32kxtal1 y6 ma9 b14 gpio_cs0 v19 32kxtal2 y4 ma10 c13 gpio_cs1 y20 kbd_col0 [xt_data] e2 ma11 a16 gpio_cs2 [[dbufrdl ]] c18 kbd_col1 [xt_clk] d1 [ma12] kbd_row6 b17 gpio_cs3 [[dbufrdh ]] d17 kbd_col2/pirq3 a2 [mcs16 ] kbd_row12 f3 gpio_cs4 [[dbufoe ]] c4 kbd_col3/pirq4 b3 memr w20 gpio_cs5 [iocs16 ] w19 kbd_col4/pirq5 c3 memw t18 gpio_cs6 [iochrdy] v18 kbd_col5/pirq6 a1 mwe a11 gpio_cs7 [pirq1] y19 kbd_col6/pirq7 b2 [pdack0 ] gpio_cs11 w17 gpio_cs8 [pirq0] w18 kbd_col7 c5 [pdack1 ] kbd_row7 d3 gpio_cs9 [tc] y18 kbd_row0 [casl2 ] b19 [pdrq0] gpio_cs12 y17 gpio_cs10 [aen] v17 kbd_row1 [casl3 ] d16 [pdrq1] kbd_row8 c2 gpio_cs11 [pdack0 ] w17 kbd_row2 [cash2 ] c17 [pe] gpio26 w2 gpio_cs12 [pdrq0] y17 kbd_row3 [cash3 ] b18 [pirq0] gpio_cs8 w18 gpio_cs13 v16 kbd_row4 [ras2 ] d15 [pirq1] gpio_cs7 y19 gpio_cs14 w16 kbd_row5 [ras3 ] c16 [pirq2] kbd_row9 e3 gpio15 y15 kbd_row6 [ma12] b17 pirq3/kbd_col2 a2 gpio16 v15 kbd_row7 [pdack1 ] d3 pirq4/kbd_col3 b3 gpio17 w15 kbd_row8 [pdrq1] c2 pirq5/kbd_col4 c3 gpio18 y14 kbd_row9 [pirq2] e3 pirq6/kbd_col5 a1
38 lan?sc400 and lansc410 microcontrollers data sheet pin designations ( pin name)lansc410 microcontroller (continued) signal name pin no. signal name pin no. signal name pin no. pirq7/kbd_col6 b2 sa12 k20 [strb ] gpio31 v2 [ppdwe ] gpio21 v3 sa13 k19 sus_res/kbd_row14 y12 [ppoen ] gpio22 t3 sa14 j20 [tc] gpio_cs9 y18 [[r32bfoe ]] kbd_row13 a3 sa15 k18 v cc a8 ras0 c15 sa16 k17 v cc a13 ras1 d14 sa17 j19 v cc a18 [ras2 ] kbd_row4 d15 sa18 h20 v cc b1 [ras3 ] kbd_row5 c16 sa19 j18 v cc b4 reserved m3 sa20 h19 v cc b16 reserved n2 sa21 g20 v cc e1 reserved p1 sa22 g19 v cc e17 reserved p3 sa23 h18 v cc g17 reserved r2 sa24 f20 v cc h1 reserved r3 sa25 h17 v cc j3 reserved t2 [sbhe ] kbd_row11 c1 v cc j17 reserved u1 sd0 [d16] g3 v cc l17 reserved v1 sd1 [d17] f2 v cc m1 reserved w5 sd2 [d18] h3 v cc m17 reset y7 sd3 [d19] g2 v cc m19 rin v11 sd4 [d20] f1 v cc n17 romcs0 r18 sd5 [d21] h2 v cc p17 romcs1 t19 sd6 [d22] g1 v cc p18 romrd v20 sd7 [d23] j2 v cc t1 romwr u19 sd8 [d24] k3 v cc u18 rstdrv v12 sd9 [d25] k2 v cc v13 rts w8 sd10 [d26] j1 v cc w9 sa0 t20 sd11 [d27] k1 v cc y1 sa1 p19 sd12 [d28] l1 v cc y16 sa2 r20 sd13 [d29] l2 v cc _a w6 sa3 n18 sd14 [d30] n1 v cc _cpu k4 sa4 p20 sd15 [d31] l3 v cc _cpu l4 sa5 n19 sin w11 v cc _cpu m4 sa6 n20 sirin y9 v cc _cpu n4 sa7 m18 sirout v8 v cc _cpu p4 sa8 m20 [slct] gpio23 u4 v cc _cpu r4 sa9 l19 [slctin ] gpio29 w3 v cc _cpu t4 sa10 l18 sout y10 v cc _rtc w7 sa11 l20 spkr v7 vl_ads c19
lan?sc400 and lansc410 microcontrollers data sheet 39 pin designations ( pin name)lansc410 microcontroller (continued) signal name pin no. signal name pin no. signal name pin no. vl_be0 f19 vl_brdy a20 vl_m/io c20 vl_be1 e20 vl_d/c e18 vl_rst b20 vl_be2 f18 vl_lclk e19 vl_w/r d18 vl_be3 d20 vl_ldev f17 [xt_clk] kbd_col1 d1 vl_blast a19 vl_lrdy d19 [xt_data] kbd_col0 e2
40 lan?sc400 and lansc410 microcontrollers data sheet pin state tables the pin state tables beginning on page 42 are grouped alphabetically by function and show pin states during reset, normal operation, and suspend mode, along with output drive strength, maximum load, supply source, and power-down groups. pin characteristics the following information describes the individual column headings in the pin state tables beginning on page 42. most abbreviations are defined in table 3. drive types and power-down groups are defined in tables 2 and 5, respectively. n pin number : the pin number column in all tables identifies the pin number of the individual i/o signal on the package. n type : the abbreviations in the type column for all tables are defined in table 2. n output drive : the output drive column designates the output drive strength of the pin. the footnote after the drive strength letter designates that the drive strength is programmable. the available drive strengths are indicated in table 2. n max load : the max load column designates the load at which the i/o timing for that pin is guaran- teed. it is also used to determine derated ac timing. n supply : the supply column identifies the v cc pin that supplies power for the specified i/o pin.the pin state table shows the pin state and termination for each power management unit mode. n normal operation : the normal operation column covers the following power management modes: C hyper-speed mode C high-speed mode C low-speed mode C temporary low-speed mode C standby mode n suspend state : the letters used in the suspend state column are defined in table 3. note that in critical suspend mode, pin terminations remain un- changed from the prior mode. table 2. drive output description output drive ioh ttl /iol ttl 1 notes: 1. the current out of a pin is given as a negative value. v cc a -3ma/3ma 3.0 v b -6ma/6ma 3.0 v c 2 2. output drive is programmable. -12ma/12ma 3.0 v d -18ma/18ma 3.0 v e 2 -24ma/24ma 3.0 v table 3. pin type abbreviations symbol meaning [ ] brackets signify alternate state { } reset configuration pin - not an output during suspend mode act pin continues to function during suspend mode b bidirectional h driven high (a logical 1) i pin is an input iod input or open drain output l driven low (a logical 0) ls last state of the pin prior to entering suspend mode na not applicable o pin is an active output od open drain output od-sti pin is typically an open drain output, but can be configured as a schmitt trigger input pd built-in pulldown resistor ppd programmable pulldown or no resistor ppu programmable pullup or no resistor ppud programmable pullup or pulldown resistor pu built-in pullup resistor s 5-v safe pin sti pin is a schmitt trigger input sti-od pin is typically a schmitt trigger input, but can be configured as an open-drain output ts three-state output
lan?sc400 and lansc410 microcontrollers data sheet 41 n power-down group : the signals on the chip are grouped together by interface for the purpose of powering down chips on the system board that are connected to these signals in suspend mode. the letters aCi in the power-down group column indi- cate the group with which each affected signal is as- sociated. only those signals that have a different suspend state based on the interface powering off have a letter. the interfaces are identified in table 5. the extended registers have bits that allow components connected to each interface to be pow- ered down in suspend mode. care must be taken when designing a system with sections that power down, because many signals are shared between components. n 5 v : an s in the 5 v column denotes pins that are 5-volt safe. this means these signals can tolerate 5 volts and they will not be damaged. however, they cannot drive to 5 volts. using the pin state tables in the following pin state tables, multiplexed pins in- clude values specific to each signal in the row (across the table) where that signal is named. if a cell has only one value listed for two or three different signals, then this value is constant (does not change) no matter what signal is programmed to come out on the pin. n for example, in the table on page 47, when pin v14 is gpio19, it is bidirectional; when pin v14 is lbl2 , it is an output only. because the cell includes two separate lines, the pin type is unique for each signal. n when the v14 pin is either gpio19 or lbl2 , the reset state is i-pu. because there is only one value shown in the table, this value applies to both signals. table 4. power pin type abbreviations symbol meaning a pin is an analog input cpu cpu power input rtc real-time clock input v cc power input table 5. power-down groups group interface a dram brom c isa (shared isa signals individually enabled) d serial port, serial irda infrared port e gpio chip selects 1C0 fvl bus g pc card socket a h pc card socket b and parallel port i sd buffer control signals
42 lan?sc400 and lansc410 microcontrollers data sheet table 6. pin state tablesystem interface 1 signal name [alternate function] pin # type output drive max load (pf) supply reset state normal operation suspend state power down group note 5 v ior u20 o c 50 v cc h o h[ts-pd][ts] c 2 s iow r19 o c 50 v cc h o h[ts-pd][ts] c 2 s memr w20 o c 50 v cc h o h[ts-pd][ts] c 2 s memw t18 o c 50 v cc h o h[ts-pd][ts] c 2 s rstdrv v12 o a 30 v cc h o ts-pd 3 sa0 t20 o cCe 4 70 v cc h o ts-pd 3 s sa1 p19 o cCe 4 70 v cc h o ts-pd 3 s sa2 r20 o cCe 4 70 v cc h o ts-pd 3 s sa3 n18 o cCe 4 70 v cc h o ts-pd 3 s sa4 p20 o cCe 4 70 v cc h o ts-pd 3 s sa5 n19 o cCe 4 70 v cc h o ts-pd 3 s sa6 n20 o cCe 4 70 v cc h o ts-pd 3 s sa7 m18 o cCe 4 70 v cc h o ts-pd 3 s sa8 m20 o cCe 4 70 v cc h o ts-pd 3 s sa9 l19 o cCe 4 70 v cc h o ts-pd 3 s sa10 l18 o cCe 4 70 v cc h o ts-pd 3 s sa11 l20 o cCe 4 70 v cc h o ts-pd 3 s sa12 k20 o cCe 4 70 v cc h o ts-pd 3 s sa13 k19 o cCe 4 70 v cc h o ts-pd 3 s sa14 j20 o cCe 4 70 v cc h o ts-pd 3 s sa15 k18 o cCe 4 70 v cc h o ts-pd 3 s sa16 k17 o cCe 4 70 v cc h o ts-pd 3 s sa17 j19 o cCe 4 70 v cc h o ts-pd 3 s sa18 h20 o cCe 4 70 v cc h o ts-pd 3 s sa19 j18 o cCe 4 70 v cc h o ts-pd 3 s sa20 h19 o cCe 4 70 v cc h o ts-pd 3 s sa21 g20 o cCe 4 70 v cc h o ts-pd 3 s sa22 g19 o cCe 4 70 v cc h o ts-pd 3 s sa23 h18 o cCe 4 70 v cc h o ts-pd 3 s sa24 f20 o b 50 v cc h o ts-pd 3 s sa25 h17 o b 50 v cc h o ts-pd 3 s sd0 [d16] g3 b [b] cCe 4 70 v cc ts-pd b-ppud i-pd 5 s sd1 [d17] f2 b [b] cCe 4 70 v cc ts-pd b-ppud i-pd 5 s sd2 [d18] h3 b [b] cCe 4 70 v cc ts-pd b-ppud i-pd 5 s sd3 [d19] g2 b [b] cCe 4 70 v cc ts-pd b-ppud i-pd 5 s sd4 [d20] f1 b [b] cCe 4 70 v cc ts-pd b-ppud i-pd 5 s sd5 [d21] h2 b [b] cCe 4 70 v cc ts-pd b-ppud i-pd 5 s sd6 [d22] g1 b [b] cCe 4 70 v cc ts-pd b-ppud i-pd 5 s sd7 [d23] j2 b [b] cCe 4 70 v cc ts-pd b-ppud i-pd 5 s sd8 [d24] k3 b [b] cCe 4 70 v cc ts-pd b-ppud i-pd 5 s sd9 [d25] k2 b [b] cCe 4 70 v cc ts-pd b-ppud i-pd 5 s sd10 [d26] j1 b [b] cCe 4 70 v cc ts-pd b-ppud i-pd 5 s
lan?sc400 and lansc410 microcontrollers data sheet 43 sd11 [d27] k1 b [b] cCe 4 70 v cc ts-pd b-ppud i-pd 5 s sd12 [d28] l1 b [b] cCe 4 70 v cc ts-pd b-ppud i-pd 5 s sd13 [d29] l2 b [b] cCe 4 70 v cc ts-pd b-ppud i-pd 5 s sd14 [d30] n1 b [b] cCe 4 70 v cc ts-pd b-ppud i-pd 5 s sd15 [d31] l3 b [b] cCe 4 70 v cc ts-pd b-ppud i-pd 5 s notes: 1. pin states for aen, iochrdy, iocs16 , pdack0 , pdrq0, tc, and pirq1Cpirq0 are listed in table 9 on page 49. pin states for bale, mcs16 , sbhe , pdack1, pdrq1 and pirq7Cpirq2 are listed in table 14 on page 53. 2. the isa control signals have three programmable options for suspend mode: Cdriven high (inactive). Cthree-stated with no pullup or pulldown. this is useful when the isa device is at 5 v and left powered in suspend. the board design should not drive 3.3-v signals into a 5-v device during suspend because this can waste power. the system designer should provide large pullup resistors to 5 v for each of these signals on the board if this configuration is programmed. C three-stated with pulldown resistors when suspended with the intent of powering off the isa device (power-down group c). be careful when handling ior and iow because they are shared with the pc card sockets and may need to be buffered if certain combinations of system components are powered up and off. summary: these pins have built-in pulldown resistors that are invoked by: Csuspend mode and the isa interface is programmed to be powered off in suspend mode (power-down group c). 3. the sa bus, sa25Csa0, and the rstdrv signal are three-stated with pulldowns in suspend mode. this accommodates having the isa bus, pc card sockets, vl bus, and rom interfaces left powered on or powered off in suspend mode. summary: these pins have built-in pulldown resistors that are invoked by: Csuspend mode. 4. c, d, and e output drives are programmable. 5. the combination of sd15Csd0 and d31Cd16 on the same pins requires the signals to be pulled up in sd bus mode (for pc compatibility) and pulled down in d bus mode (for consistency with d15Cd0). regardless of the mode the bus is in, the pins are in the input state (i.e., they are still bidirectional and are not driven as outputs) and pulled down in suspend mode. these signals are pulled up or down automatically depending on whether the sd buffer is enabled or not (cfg3), and whether the system is in suspend mode or not. summary: these pins have built-in pulldown and pullup resistors that are invoked by: Creset invokes the pulldown resistors. Csuspend mode invokes the pulldown resistors. Coperating (hyper/high/low/temp low-speed modes): the pins will have pullups if the sd buffer control signals are enabled, and have pulldowns otherwise. table 6. pin state tablesystem interface 1 (continued) signal name [alternate function] pin # type output drive max load (pf) supply reset state normal operation suspend state power down group note 5 v
44 lan?sc400 and lansc410 microcontrollers data sheet table 7. pin state tablememory interface 1 signal name [alternate function] pin # type output drive max load (pf) supply reset state normal operation suspend state power down group note 5 v cash0 d13 o d 30 v cc h o o[l][ts-pd] a 2 cash1 a17 o d 30 v cc h o o[l][ts-pd] a 2 casl0 b15 o d 30 v cc h o o[l][ts-pd] a 2 casl1 c14 o d 30 v cc h o o[l][ts-pd] a 2 d0 b10 b cCe 3 70 v cc ts-pd b-pd ts-pd 4 d1 a10 b cCe 3 70 v cc ts-pd b-pd ts-pd 4 d2 c9 b cCe 3 70 v cc ts-pd b-pd ts-pd 4 d3 b9 b cCe 3 70 v cc ts-pd b-pd ts-pd 4 d4 a9 b cCe 3 70 v cc ts-pd b-pd ts-pd 4 d5 b8 b cCe 3 70 v cc ts-pd b-pd ts-pd 4 d6 c8 b cCe 3 70 v cc ts-pd b-pd ts-pd 4 d7 a7 b cCe 3 70 v cc ts-pd b-pd ts-pd 4 d8 b7 b cCe 3 70 v cc ts-pd b-pd ts-pd 4 d9 a6 b cCe 3 70 v cc ts-pd b-pd ts-pd 4 d10 c7 b cCe 3 70 v cc ts-pd b-pd ts-pd 4 d11 b6 b cCe 3 70 v cc ts-pd b-pd ts-pd 4 d12 a5 b cCe 3 70 v cc ts-pd b-pd ts-pd 4 d13 c6 b cCe 3 70 v cc ts-pd b-pd ts-pd 4 d14 b5 b cCe 3 70 v cc ts-pd b-pd ts-pd 4 d15 a4 b cCe 3 70 v cc ts-pd b-pd ts-pd 4 kbd_row0 [casl2 ] b19 sti-od [o] d250v cc i-pu iod-pu o i-pu o[l][ts-pd] a 2 kbd_row1 [casl3 ] d16 sti-od [o] d250v cc i-pu iod-pu o i-pu o[l][ts-pd] a 2 kbd_row2 [cash2 ] c17 sti-od [o] d250v cc i-pu iod-pu o i-pu o[l][ts-pd] a 2 kbd_row3 [cash3 ] b18 sti-od [o] d250v cc i-pu iod-pu o i-pu o[l][ts-pd] a 2 kbd_row4 [ras2 ] d15 sti-od [o] cCe 3 250 v cc i-pu iod-pu o i-pu o[l][ts-pd] a 2 kbd_row5 [ras3 ] c16 sti-od [o] cCe 3 250 v cc i-pu iod-pu o i-pu o[l][ts-pd] a 2 kbd_row6 [ma12] b17 sti-od [o] cCe 3 250 v cc i-pu iod-pu o i-pu ts-pd 5 ma0 {cfg0} c10 o {i} cCe 3 70 v cc i-pd o ts-ppd 6 ma1 {cfg1} b11 o {i} cCe 3 70 v cc i-pd o ts-ppd 6 ma2 {cfg2} a12 o {i} cCe 3 70 v cc i-pd o ts-ppd 6, 7 ma3 {cfg3} b12 o {i} cCe 3 70 v cc i-pd o ts-ppd 6 ma4 c11 o cCe 3 70 v cc i-pd o ts-pd 6, 8 ma5 a14 o cCe 3 70 v cc l o ts-pd 8 ma6 b13 o cCe 3 70 v cc l o ts-pd 8 ma7 c12 o cCe 3 70 v cc l o ts-pd 8 ma8 a15 o cCe 3 70 v cc l o ts-pd 8 ma9 b14 o cCe 3 70 v cc l o ts-pd 8
lan?sc400 and lansc410 microcontrollers data sheet 45 ma10 c13 o cCe 3 70 v cc l o ts-pd 8 ma11 a16 o cCe 3 70 v cc l o ts-pd 8 mwe a11 o cCe 3 70 v cc h o h[ts-pd] a 2 ras0 c15 o cCe 3 50 v cc h o o[l][ts-pd] a 2 ras1 d14 o cCe 3 50 v cc h o o[l][ts-pd] a 2 romcs0 r18 o b 50 v cc h o h[ts-pd][ts] b 9 s romcs1 t19 o b 50 v cc h o h[ts-pd][ts] b 9 s romrd v20 o b 50 v cc h o h[ts-pd][ts] b 9 s romwr u19 o b 50 v cc h o h[ts-pd][ts] b 9 s notes: 1. pin states for d31Cd16 are listed in table 6 on page 42. 2. ras 3 Cras 0 , cash 3 Ccash 0 , casl 3 Ccasl 0 , and mwe suspend state of the pins: Cthe ras and cas signals remain active if the dram interface is configured for cas -before-ras refresh in suspend mode. Cthe ras and cas signals will be low if the dram is configured for self-refresh in suspend mode. Cwill be three-stated with a pulldown resistor if the dram interface is programmed to be disabled so the dram can be powered down (power-down group a). Cwill not be affected by this when the ras and cas signals that share pins with other functions (ras3 Cras2 , cash3 C cash2 , and casl3 Ccasl2 ) are not enabled to come out of the chip. Cthe mwe signal will be driven out high (deasserted) when the dram is programmed to be left powered (power-down group a). summary: these pins have built-in pulldown resistors that are invoked by: Csuspend mode and dram interface programmed for power-down in suspend (power-down group a), and the pins are enabled as ras/cas for ras 3 Cras 2 , cash 3 Ccash 2 , and casl 3 Ccasl 2 . 3. c, d, and e output drives are programmable. 4. the data bus d15Cd0 has built-in pulldown resistors that are invoked when the data bus signals are inputs. 5. memory address ma12 suspend state of the pin: will be three-stated with a pulldown resistor. this will work for cas -before-ras refresh, self-refresh, and the dram powered down. summary: this pin has a built-in pulldown resistor that is invoked by suspend mode. 6. memory address ma4Cma0 pins are shared with the power-on configuration signals so the reset state of the pins has a pull- down resistor on these signals. this default configuration will choose: not test mode and an 8-bit rom/flash memory accessed by romcs0 with the sd buffer-control signals disabled. the pulldown resistors are from 50 k to 150 k; they need to be overridden by pullup resistors on the board if other configurations are needed. these pulldown resistors are disabled after reset; they are not active during normal chip operation. for configuration signals cfg0, cfg1, cfg2, and cfg3, if the system uses the default configuration, the pulldown resistors will be active again in suspend mode. if external pullup resistors are used on the board for a different configuration, the pin s with external pullups will three-state in suspend mode without pulldown resistors. the reserved signal on ma4 is only used for amd testing; it should not be pulled up on the system design. this pin will always go to three-state with a pulldown resistor in suspend mode. summary: each pin has a built-in pulldown resistor that is invoked by: Creset Csuspend mode and the configuration pin being low during reset (for cfg3Ccfg0). Csuspend mode for the reserved signal on ma4. table 7. pin state tablememory interface 1 (continued) signal name [alternate function] pin # type output drive max load (pf) supply reset state normal operation suspend state power down group note 5 v
46 lan?sc400 and lansc410 microcontrollers data sheet 7. the cfg2 pin is not supported on the lansc410 microcontroller. 8. memory address ma11Cma4 suspend state of the pins: will be three-stated with a pulldown resistor. this will work for cas -before-ras refresh, self-refresh, and the dram powered down. summary: these pins have built-in pulldown resistors that are invoked by suspend mode. 9. the rom control signals have three programmable options for suspend mode: Cdriven high (inactive) Cthree-stated with no pullup or pulldown. this is useful when the rom is at 5 v and left powered in suspend. the board design should not drive 3.3-v signals into a 5-v device during suspend, because this can waste power. the system designer could provide large pullup resistors to 5 v for each of these signals on the board if this configuration is programmed. C three-stated with pulldown resistors when suspended with the intent of powering off the roms (power-down group b). summary: these pins have built-in pulldown resistors that are invoked by: Csuspend mode; and the rom interface is programmed to be powered off in suspend mode (power-down group b).
lan?sc400 and lansc410 microcontrollers data sheet 47 table 8. pin state tablegpios/parallel port/pc card socket b signal name [alternate function] pin # type output drive max load (pf) supply reset state normal operation suspend state power down group note 5 v gpio15 [pcma_vpp2] y15 b [o] b50v cc i-pd i-ppd[o] o i-ppd[o] o 1,2 gpio16 [pcmb_vcc ] v15 b [o] b50v cc i-pd i-ppd[o] o i-ppd[o] o 1, 2 gpio17 [pcmb_vpp1] w15 b [o] b50v cc i-pd i-ppd[o] o i-ppd[o] o 1, 2 gpio18 [pcmb_vpp2] y14 b [o] b50v cc i-pd i-ppd[o] o i-ppd[o] o 1, 2 gpio19 [lbl2 ] v14 b [o] b50v cc i-pu i-ppu[o] o i-ppu[o] o 1 gpio20 [cd_a2] g18 b [i] b50v cc i-pu i-ppu[o] i-ppu i-ppu[o] i-ppud g 1, 2 s gpio21 [ppdwe ] (pc card enabled) v3 b [o] c30v cc i-pu i-ppu[o] o ts-pd i-ppu[o] h[ts-pd][ts] ts-pd h 3 s gpio22 [ppoen] (pc card enabled) t3 b [o] c30v cc i-pu i-ppu[o] o ts-pd i-ppu[o] h[ts-pd][ts] ts-pd h 3 s gpio23 [slct] [wp_b] u4 b [i] [i] d150v cc i-pu i-ppu[o] i-pu i-ppu i-ppu[o] i-pu[i-pd] i-ppud h 2, 3 s gpio24 [busy] [bvd2_b] u3 b [i] [i] d150v cc i-pu i-ppu[o] i-pu i-ppu i-ppu[o] i-pu[i-pd] i-ppud h 2, 3 s gpio25 [ack ] [bvd1_b] u2 b [i] [i] d150v cc i-pu i-ppu[o] i-pu i-ppu i-ppu[o] i-pu[i-pd] i-ppud h 2, 3 s gpio26 [pe] [rdy_b ] w2 b [i] [i] d150v cc i-pu i-ppu[o] i-pu i-ppu i-ppu[o] i-pu[i-pd] i-ppud h 2, 3 s gpio27 [error ] [cd_b ] v4 b [i] [i] d150v cc i-pu i-ppu[o] i-pu i-ppu i-ppu[o] i-pu[i-pd] i-ppud h 2, 3 s gpio28 [init ] [reg_b ] y2 b [od][o] [o] d150v cc od-pu i-ppu[o] od-pu[o] o i-ppu[o] od-pu[od-pd] h[ts-pd][ts] h 2, 3 s gpio29 [slctin] [rst_b] w3 b [od][o] [o] d150v cc od-pu i-ppu[o] od-pu[o] o i-ppu[o] od-pu[od-pd] l[ts-pd] h 2, 3 s gpio30 [afdt ] [mceh_b ] w1 b [od][o] [o] d150v cc od-pu i-ppu[o] od-pu[o] o i-ppu[o] od-pu[od-pd] h[ts-pd][ts] h 2, 3 s gpio31 [strb ] [mcel_b ] v2 b [od][o] [o] d150v cc od-pu i-ppu[o] od-pu[o] o i-ppu[o] od-pu[od-pd] h[ts-pd][ts] h 2, 3 s gpio_cs13 [pcma_vcc ] v16 b [o] b50v cc i-pd i-ppd[o] o i-ppd[o] o 1, 2 gpio_cs14 [pcma_vpp1] w16 b [o] b50v cc i-pd i-ppd[o] o i-ppd[o] o 1, 2
48 lan?sc400 and lansc410 microcontrollers data sheet notes: 1. the shared gpio20Cgpio15, gpio_cs14Cgpio_cs13, and pc card battery signals: as gpio_csxs, the signals are active in suspend mode: that is, if they are inputs before suspend, they are still inputs during suspend (the gpio_css can be used to wake up the system); if they are outputs before suspend, they are still outputs during suspend (the gpio_css can be programmed to change state by mode). as inputs, the pullup or pulldown on the signal can be disabled; if disabled, it is disabled in all modes. when the signal is an output, the built-in resistors are automatically disa bled. when enabled, the latched battery low detect function (lbl2 ) that is shared on gpio19 is an output in all modes; there are no pullup or pulldown resistors active. on the lansc400 microcontroller, the pc card functions shared on these pins are programmable by pc card socket; the pin multiplexing options are explained earlier in this document. for the pc card power control (pcma_vcc , pcma_vpp1, pcma_vpp2, pcmb_vcc , pcmb_vpp1, pcmb_vpp2), the signals are outputs for each mode. for the second card detect (cd_a2 ): Creset invokes pullup. Cduring normal operation, the pullup resistor can be disabled by a register bit. Cduring suspend mode, the input will have a pulldown if the pc card socket a interface is programmed to be powered off in suspend mode (power-down group g). if the socket is not programmed to be powered off in suspend mode, the input will have the same state as when operating: the pullup is programmable to be enabled or not. 2. the pc card signals mcel_b , mceh_b , rst_b, reg_b , cd_b , rdy_b , bvd1_b, bvd2_b, wp_b, cd_a2 , pcmb_vpp2, pcmb_vpp1, pcmb_vcc , pcma_vpp1, pcma_vpp2, and pcma_vcc are not supported on the lansc410 microcontroller. 3. the shared parallel port, pc card socket b control, and gpio signals: Cthese signals default to the gpio interface on reset. Cas a parallel port in suspend mode, these signals are programmable to accommodate the parallel port powered up or down. Cas pc card control on the lansc400 microcontroller, these signals have the same features as the socket a control signals. Cas gpios, these signals are not handled specially in suspend, they remain the same as they were when the chip was active (i.e., they remain as inputs with the pullup enabled or not, or continue to drive out the same value if they were outputs). summary: shared parallel port/pc card socket b/gpio signals: built-in pullup and pulldown resistors that are invoked by: Creset invokes pullups Cas parallel port signals: ?operating: pullups are enabled if not epp mode. outputs without pullup or pulldowns if epp mode. ?suspend: pullups are enabled, unless the parallel port is programmed to be powered off in suspend mode, in which case pulldowns are enabled. ?if epp mode is enabled for the parallel port, the outputs are driven out at their last value in suspend mode. Cas pc card socket b signals (lansc400 microcontroller only): ?operating: outputs have no pullups or pulldowns; inputs have pullups that can be disabled by programming a bit. ?suspend: outputs are driven out inactive with no pullups or pulldowns unless the pc card socket b is programmed to be powered off in suspend mode; then the outputs go to three-state with pulldown resistors; inputs will be the same as they were when operating, with a pullup resistor that can be disabled by programming, unless the pc card socket b is programmed to be powered off in suspend mode (power-down group h), in which case the inputs have pulldown resistors enabled. Cas gpio signals: ?operating or suspend: as outputs they have no pullups or pulldowns; as inputs they have pullups that can be dis- abled by programming a bit; no change of state when the system goes to suspend.
lan?sc400 and lansc410 microcontrollers data sheet 49 table 9. pin state tablegpios/isa bus signal name [alternate function] pin # type output drive max load (pf) supply reset state normal operation suspend state power down group note 5 v gpio_cs5 [iocs16 ] w19 b [i] b50v cc i-pu i-ppu[o] i-pu i-ppu[o] i-pu[i-pd] c 1 s gpio_cs6 [iochrdy] v18 b [sti] b50v cc i-pu i-ppu[o] i-pu i-ppu[o] i-pu[i-pd] c 1 s gpio_cs7 [pirq1] y19 b [i] b50v cc i-pu i-ppu[o] i-pu i-ppu[o] i-pu[i-pd] c 1 s gpio_cs8 [pirq0] w18 b [i] b50v cc i-pu i-ppu[o] i-pu i-ppu[o] i-pu[i-pd] c 1 s gpio_cs9 [tc] y18 b [o] c50v cc i-pu i-ppu[o] o i-ppu[o] ts-pd 1 s gpio_cs10 [aen] v17 b [o] c50v cc i-pu i-ppu[o] o i-ppu[o] ts-pd 1 s gpio_cs11 [pdack0 ] w17 b [o] c50v cc i-pu i-ppu[o] o i-ppu[o] h[ts-pd][ts] c 1 s gpio_cs12 [pdrq0] y17 b [i] b50v cc i-pd i-ppd[o] i-pd i-ppd[o] i-pd 1 s
50 lan?sc400 and lansc410 microcontrollers data sheet notes: 1. the shared gpio_cs12Cgpio_cs5 and isa signals: as gpio_cs signals, they are active in suspend mode: that is, if they are inputs before suspend, they are still inputs during suspend (they can be used to wake up the system); if they are outputs before suspend, they are still outputs during suspend (they can be programmed to change state by mode). as inputs, the pullup or pulldown on the signal can be disabled; if disabled, it is disabled in all modes. when the signal is an output, the built-in resistors are automatically disabled. the isa function for each pin is programmable by functional group: that is, the system can choose to use pirq0 and still use the dma pins as gpio_csxs (the pin multiplexing options are explained elsewhere in this document). as isa signals, these pins are programmable to support a system with isa peripherals powered up or down in suspend mode (power-down group c). for those signals that are high when deasserted, there is an option to three-state them with no built-in resistors, so an external resistor can be placed on the board to pull them up to 5 v. summary: gpio_cs12: built-in pulldown resistor that is invoked by: Creset Cisa signal enabled on this pin (the pin will be pdrq0). Cthe pulldown is disabled by this pin being a gpio_cs and an output. Cthe pulldown can be programmed to be disabled when the pin is a gpio_cs input. summary: gpio_cs11: built-in pullup and pulldown resistors that are invoked by: Creset invokes the pullup. Cwhen enabled as the isa signal pdack0 : ?in normal operation, this signal is an output and no pullup or pulldown is needed. ?the pulldown is invoked by suspend mode and the isa bus is programmed to be powered off in suspend (power- down group c). ?if the isa bus is programmed for 5-v use and is not powered down in suspend, then this signal is three-state without a built-in pullup or pulldown resistor. Cwhen enabled as the gpio_cs11 signal: ?as an output, the pullup and pulldown are disabled in all modes, and these gpio_csx signals can be active in suspend. ?as an input, the pullup can be programmed to be enabled or disabled; this will then be the state of the pin in all modes, including suspend. summary: gpio_cs10Cgpio_cs9: built-in pullup and pulldown resistors that are invoked by: Creset invokes the pullups. Cwhen enabled as the isa signals aen and tc: ?in normal operation, these signals are outputs and no pullup or pulldown is needed. ?the pulldowns are invoked by suspend mode. Cwhen enabled as the gpio_cs10Cgpio_cs9 signals: ?as an output, the pullup and pulldown are disabled in all modes, and these gpio_cs signals can be active in suspend. ?as an input, the pullup can be programmed to be enabled or disabled; this will then be the state of the pin in all modes, including suspend. summary: gpio_cs8Cgpio_cs5: built-in pullup and pulldown resistors that are invoked by: Creset invokes the pullups. Cwhen enabled as pirq1Cpirq0, iochrdy, and iocs16 : ?in normal operation and suspend, these signals are inputs and the pullup resistors are active. ?the pulldowns are invoked by suspend mode and the isa bus interface programmed for power off in suspend (power-down group c). Cwhen enabled as the gpio_cs8Cgpio_cs5 signals: ?as an output, the pullup and pulldown are disabled in all modes, and these gpio_csx signals can be active in suspend. ?as an input, the pullup can be programmed to be enabled or disabled; this will then be the state of the pin in all modes, including suspend.
lan?sc400 and lansc410 microcontrollers data sheet 51 table 10. pin state tablegpios/system data (sd) buffer control signal name [alternate function] pin # type output drive max load (pf) supply reset state normal operation suspend state power down group note 5 v gpio_cs2 [[dbufrdl ]] c18 b [[o]] c50v cc i-pu i-ppu[o] o i-ppu[o] ts-pd 1 gpio_cs3 [[dbufrdh ]] d17 b [[o]] c50v cc i-pu i-ppu[o] o i-ppu[o] ts-pd 1 gpio_cs4 [[dbufoe ]] c4 b [[o]] c50v cc i-pu i-ppu[o] o i-ppu[o] h[ts-pd][ts] i 1 s kbd_row13 [[r32bfoe ]] a3 sti-od [o] c250v cc i-pu iod-pu o i-pu h[ts-pd][ts] i 2 s notes: 1. the data buffer control signals are shared with the gpio_cs4Cgpio_cs2 signals and with the keyboard row signal: when the data buffer control signals are enabled on the pins, they will drive inactive during suspend mode, go three-state without resistors to allow an external resistor to 5 v, or three-state with a pulldown to support powering off the data buffer. summary: gpio_cs4Cgpio_cs2/dbufoe /dbufrdh /dbufrdl : built-in pullup and pulldown resistors that are invoked by: Creset invokes pullup. Cwhen buffer control is invoked by the configuration pin, these pins are outputs without any pullups or pulldowns. Cwhen buffer control is enabled and in suspend mode, dbufrdh and dbufrdl are three-state with the pulldowns enabled; dbufoe has three options: ?high (inactive) with no pullup or pulldown. ?three-state with a pulldown if it is programmed for the buffer to be powered off in suspend mode (power-down group i). ?three-state with no pulldown if it is programmed for the buffer to be powered on in suspend mode and at 5 v. Cwhen enabled as the gpio_cs4Cgpio_cs2 signals: ?as an output, the pullup and pulldown are disabled in all modes, and these gpio_cs signals can be active in suspend. ?as an input, the pullup can be programmed to be enabled or disabled. this will then be the state of the pin in all modes, including suspend. 2. this data buffer control signal (r32bfoe ) is shared with the keyboard row signal: when the data buffer control signals are enabled on the pins, they will drive inactive during suspend mode, go three-state without resistors to allow an external resistor to 5 v, or three-state with a pulldown to support powering off the data buffer. summary: kbd_row13/r32bfoe : built-in pullup and pulldown resistors that are invoked by: Creset invokes the pullup. Cas r32bfoe , this pin is an output without a pullup or pulldown. Cwhen buffer control is enabled and in suspend mode, r32bfoe has three options: ?high (inactive) with no pullup or pulldown. ?three-state with a pulldown if it is programmed for the buffer to be powered off in suspend mode. ?three-state with no pulldown if it is programmed for the buffer to be powered on in suspend mode and at 5 v. Cwhen enabled as the keyboard row signal, this signal has a pullup enabled at all times.
52 lan?sc400 and lansc410 microcontrollers data sheet table 11. pin state tablegpios signal name [alternate function] pin # type output drive max load (pf) supply reset state normal operation suspend state power down group note 5 v gpio_cs0 v19 b b 50 v cc i-pu i-ppu[o] i-ppu[o] e 1 s gpio_cs1 y20 b b 50 v cc i-pu i-ppu[o] i-ppu[o] e 1 s notes: 1. the gpio_cs signals become inputs in suspend mode with either a pullup resistor for devices that are left powered, or a pulldown resistor for devices that are to be powered off. summary: gpio_cs1Cgpio_cs0: built-in pullup and pulldown resistors that are invoked by: reset invokes pullup. when enabled as the gpio_cs1Cgpio_cs0 signals: as an output, the pullup and pulldown are disabled in all modes, and these gpio_csxs can be active in suspend. as an input, the pullup can be programmed to be enabled or disabled; this will then be the state of the pin in all modes, including suspend. table 12. pin state tableserial port signal name [alternate function] pin # type output drive max load (pf) supply reset state normal operation suspend state power down group note 5 v cts v10 i v cc i-pu i-pu [i-pd] i-pu[i-pd] d 1 notes: 1. the serial port output signals are three-state with built-in pulldown resistors in suspend mode. the serial port input signa ls can be left as inputs with pullups for a suspend when the serial device is left powered. or, they can be configured as inputs with pulldown resistors if the serial device is to be powered off (power-down group d). summary: the serial port output pins have built-in pulldown resistors that are invoked by suspend mode. summary: the serial port input pins have built-in pullup and pulldown resistors that are invoked by: Creset invokes the pullup resistors. Coperating: the pullup resistors are enabled. Csuspend mode invokes the pulldown resistors if the serial interface is programmed to be powered off in suspend (power- down group c); otherwise there are pullup resistors in suspend mode. dcd v9 i v cc i-pu i-pu [i-pd] i-pu[i-pd] d 1 dsr w10 i v cc i-pu i-pu [i-pd] i-pu[i-pd] d 1 dtr y8 o a 30 v cc h o [ts-pd] ts-pd 1 rin v11 i v cc i-pu i-pu [i-pd] i-pu[i-pd] d 1 rts w8 o a 30 v cc h o [ts-pd] ts-pd 1 sin w11 i v cc i-pu i-pu [i-pd] i-pu[i-pd] d 1 sout y10 o a 30 v cc h o [ts-pd] ts-pd 1 table 13. pin state tableinfrared interface signal name [alternate function] pin # type output drive max load (pf) supply reset state normal operation suspend state power down group note 5 v sirin y9 i v cc i-pd i-ppd i-ppd 1 notes: 1. the serial infrared interface output and input settle to suspend states that allow the device to be powered up or off. the o utput is three-state with a built-in pulldown resistor, and the input has a built-in pulldown resistor. the pulldown resistor on the input pin (sirin) can be programmed to be disabled during normal operation and suspend mode. summary: the serial infrared input pin has a built-in pulldown resistor that is invoked by: Creset invokes the pulldown resistor. Cthe pulldown resistor is then programmable to be there or not. sirout v8 o a 30 v cc l o ts-pd 1
lan?sc400 and lansc410 microcontrollers data sheet 53 table 14. pin state tablekeyboard interface signal name [alternate function] pin # type output drive max load (pf) supply reset state normal operation suspend state power down group note 5 v kbd_col0 [xt_data] e2 od-sti [b] d250v cc od- pu iod-ppud iod-ppud iod-ppud iod-ppud 1 s kbd_col1 [xt_clk] d1 od-sti [b] d250v cc od- pu iod-ppud iod-ppud iod-ppud iod-ppud 1 s kbd_col2/ pirq3 a2 od-sti [i] d250v cc od- pu iod-ppud i-ppud iod-ppud i-ppud[i-pd] c 1 s kbd_col3/ pirq4 b3 od-sti [i] d250v cc od- pu iod-ppud i-ppud iod-ppud i-ppud[i-pd] c 1 s kbd_col4/ pirq5 c3 od-sti [i] d250v cc od- pu iod-ppud i-ppud iod-ppud i-ppud[i-pd] c 1 s kbd_col5/ pirq6 a1 od-sti [i] d250v cc od- pu iod-ppud i-ppud iod-ppud i-ppud[i-pd] c 1 s kbd_col6/ pirq7 b2 od-sti [i] d250v cc od- pu iod-ppud i-ppud iod-ppud i-ppud[i-pd] c 1 s kbd_col7 c5 od-sti d 250 v cc od- pu iod-ppud iod-ppud 1 kbd_row0 [casl2 ] b19 sti-od [o] d250v cc i-pu iod-pu o i-pu o[l][ts-pd] a 2 kbd_row1 [casl3 ] d16 sti-od [o] d250v cc i-pu iod-pu o i-pu o[l][ts-pd] a 2 kbd_row2 [cash2 ] c17 sti-od [o] d250v cc i-pu iod-pu o i-pu o[l][ts-pd] a 2 kbd_row3 [cash3 ] b18 sti-od [o] d250v cc i-pu iod-pu o i-pu o[l][ts-pd] a 2 kbd_row4 [ras2 ] d15 sti-od [o] p-c,e 250 v cc i-pu iod-pu o i-pu o[l][ts-pd] a 2 kbd_row5 [ras3 ] c16 sti-od [o] p-c,e 250 v cc i-pu iod-pu o i-pu o[l][ts-pd] a 2 kbd_row6 [ma12] b17 sti-od [o] p-c,e 250 v cc i-pu iod-pu o i-pu ts-pd 3 kbd_row7 [pdack1 ] d3 sti-od [o] c250v cc i-pu iod-pu o i-pu h[ts-pd][ts] c s kbd_row8 [pdrq1] c2 sti-od [i] c250v cc i-pu iod-pu i-pd i-pu i-pd s kbd_row9 [pirq2] e3 sti-od [i] c250v cc i-pu iod-pu i-pu i-pu i-pu[i-pd] c s kbd_row10 [bale] d2 sti-od [o] c250v cc i-pu iod-pu o i-pu ts-pd s kbd_row11 [sbhe ] c1 sti-od [o] c250v cc i-pu iod-pu o i-pu h[ts-pd][ts] c s kbd_row12 [mcs16 ] f3 sti-od [i] c250v cc i-pu iod-pu i-pu i-pu i-pu[i-pd] c s kbd_row13 [[r32bfoe ]] a3 sti-od [o] c250v cc i-pu iod-pu o i-pu h[ts-pd][ts] i 4 s
54 lan?sc400 and lansc410 microcontrollers data sheet notes: 1. the keyboard column signals are shared with the programmable irqs and xt keyboard signals. as keyboard column signals and xt keyboard signals, they are inputs and open drain outputs with pullup or pulldown resistors in normal operation and suspend mode. each column signal is individually programmable for the pullup or pulldown in the keyboard extended registers. as irqs, the pins are inputs with built-in pullup or pulldown resistors (use the same registers in the keyboard controller to enable pullups or pulldowns). during suspend mode, they stay as inputs with the pullup or pulldown. or, if power-down group c is enabled for the isa bus to be powered down in suspend mode and a bit is set identifying that these signals are being used as irqs, they will have pulldown resistors activated. there is no programmable bit to make these signals irqs beyond the extended register in the interrupt controller that maps the pin to a particular irq. if the system must use any of these as irqs, a bit must be set, notifying the chip, so that they can have the pulldown resistors invoked in suspend mode. summary: as keyboard column and xt keyboard signals: Cpullup or pulldown resistor depending on the setting of the keyboard column pullup/pulldown register in the keyboard controller. summary: as programmable irq signals: Cpullup or pulldown resistors during normal operation and suspend (depending on the configuration register in the keyboard controller. Cpulldown resistors during suspend if power-down group c (the isa bus) is enabled for power-down in suspend, and a bit is set indicating that these signals are used as irqs and need to be pulled down in suspend. 2. ras 3 Cras 2 , cash 3 Ccash 2 , and casl 3 Ccasl 2 suspend state of the pins: Cthe ras and cas signals remain active if the dram interface is configured for cas -before-ras refresh in suspend mode. Cthe ras and cas signals will be low if the dram is configured for self-refresh in suspend mode. Cwill be three-stated with a pulldown resistor if the dram interface is programmed to be disabled so the dram can be powered down (power-down group a). Cwill not be affected by this when the ras and cas signals that share pins with other functions are not enabled to come out of the chip. summary: these pins have built-in pulldown resistors that are invoked by: Csuspend mode and dram interface programmed for power-down in suspend (power-down group a), and the pins are enabled as ras /cas for ras 3 Cras 2 , cash 3 Ccash 2 , and casl 3 Ccasl 2 . 3. memory address ma12 suspend state of the pin: will be three-stated with a pulldown resistor. this will work for cas -before-ras refresh, self-refresh, and the dram powered down. summary: this pin has a built-in pulldown resistor that is invoked by suspend mode. 4. the data buffer control signal r32bfoe that is shared with the keyboard row signal: when the data buffer control signals are enabled on the pins, they will drive inactive during suspend mode, go three-state without resistors to allow an external resistor to 5 v, or three-state with a pulldown to support powering off the data buffer. summary: kbd_row13/r32bfoe : built-in pullup and pulldown resistors that are invoked by: Creset invokes the pullup. Cas r32bfoe , this pin is an output without a pullup or pulldown. Cwhen buffer control is enabled and in suspend mode, r32bfoe has three options: ?high (inactive) with no pullup or pulldown. ?three-state with a pulldown if it is programmed for the buffer to be powered off in suspend mode. ?three-state with no pulldown if it is programmed for the buffer to be powered on in suspend mode and at 5 v. Cwhen enabled as the keyboard row signal, this signal has a pullup enabled at all times.
lan?sc400 and lansc410 microcontrollers data sheet 55 table 15. pin state tablepc card socket a signal name [alternate function] pin # type output drive max load (pf) supply reset state normal operation suspend state power down group note 5 v bvd1_a v1 i v cc i-pu i-ppu i-ppud g 1,2 notes: 1. on the lansc400 microcontroller only, the pc card control signals for socket a: the pullup resistors for the input signals are built in and can be disabled if external pullups are necessary (the external pul lups can be on a different power plane). in suspend mode, the signals can be configured for: a card not plugged in (inputs terminated with internal resistors), a card plugged in and powered (the output signals drive out inactive), a card plugged in and powered and at 5 v (the inactive high output signals are three-stated and pullup resistors should be put on the board), and a card plugged in and powered off (the signals terminated with pulldown resistors) (power-down group g). summary: the outputs are built-in pulldown resistors that are invoked by: Csuspend and pc card socket a is programmed to be powered off in suspend (power-down group g). Cthese are not pulldowns for normal operation. these are driven outputs. summary: the inputs are built-in pullup and pulldown resistors that are invoked by: Creset invokes pullups. Cduring normal operation, the pullup resistors can be disabled by a register bit. Cduring suspend mode, the inputs will have pulldowns if the pc card socket a interface is programmed to be powered off in suspend mode (power-down group g). if the socket is not programmed to be powered off in suspend mode, the inputs have the same state as when operating: the pullups are programmable to be enabled or not. 2. the pc card signals mcel_a , mceh_a , rst_a, reg_a , cd_a , rdy_a , bvd1_a, bvd2_a, wp_a, wait_ab , oe , we , and icdir are not supported on the lansc410 microcontroller. s bvd2_a r3 i v cc i-pu i-ppu i-ppud g 1, 2 s cd_a r2 i v cc i-pu i-ppu i-ppud g 1, 2 s icdir m3 o b 50 v cc l o h[ts-pd][ts] g 1, 2 s mceh_a [[bndscn_tms]] n3 o [[i]] b50v cc ho [i-pd] h[ts-pd][ts] g 1, 2 s mcel_a [[bdnscn_tck]] p2 o [[i]] b50v cc ho [i-pd] h[ts-pd][ts] g 1, 2 s oe p1 o b 50 v cc h o h[ts-pd][ts] g 1, 2 s rdy_a p3 i v cc i-pu i-ppu i-ppud g 1, 2 s reg_a [[bndscn_tdo]] m2 o [[o]] b50v cc ho [o] h[ts-pd][ts] g 1, 2 s rst_a [[bndscn_tdi]] r1 o [[i]] b50v cc oo [i-pd] l[ts-pd] g 1, 2 s wait_ab u1 i v cc i-pu i-ppu i-ppud g 1, 2 s we n2 o b 50 v cc h o h[ts-pd][ts] g 1, 2 s wp_a t2 i v cc i-pu i-ppu i-ppud g 1, 2 s
56 lan?sc400 and lansc410 microcontrollers data sheet table 16. pin state tablegraphics controller/vesa local bus control signal name [alternate function] pin # type output drive max load (pf) supply reset state normal operation suspend state power down group note 5 v frm [vl_lclk] e19 o [o] e150v cc ts-pd o[ts-pd] o[ts-pd] ts-pd ts-pd f 1,2 s lc [vl_be1 ] e20 o [o] d150v cc ts-pd o[ts-pd] o[ts-pd] ts-pd h[ts-pd] f 1,2 s lcdd0 [vl_rst ] b20 o [o] d150v cc ts-pd o[ts-pd] o[ts-pd] ts-pd h[ts-pd] f 1,2 s lcdd1 [vl_ads ] c19 o [o] d150v cc ts-pd o[ts-pd] o[ts-pd] ts-pd h[ts-pd] f 1,2 s lcdd2 [vl_w/r ] d18 o [o] d150v cc ts-pd o[ts-pd] o[ts-pd] ts-pd h[ts-pd] f 1,2 s lcdd3 [vl_m/io ] c20 o [o] d150v cc ts-pd o[ts-pd] o[ts-pd] ts-pd h[ts-pd] f 1,2 s lcdd4 [vl_lrdy ] d19 o [i] d150v cc ts-pd ts-pd[o] i ts-pd i[i-pd] f 1,2 s lcdd5 [vl_d/c ] e18 o [o] d150v cc ts-pd o[ts-pd] o[ts-pd] ts-pd h[ts-pd] f 1,2 s lcdd6 [vl_ldev ] f17 o [i] d150v cc ts-pd ts-pd[o] i ts-pd i[i-pd] f 1,2 s lcdd7 [vl_be3 ] d20 o [o] d150v cc ts-pd o[ts-pd] o[ts-pd] ts-pd h[ts-pd] f 1,2 s lvdd [vl_blast ] a19 o [o] d50v cc ts-pu o[ts-pu] o[ts-pu] h h[ts-pd] f 1,2 lvee [vl_brdy ] a20 o [i] d50v cc ts-pu o[ts-pu] i h i[i-pd] f 1,2 m [vl_be2 ] f18 o [o] d150v cc ts-pd o[ts-pd] o[ts-pd] ts-pd h[ts-pd] f 1,2 s sck [vl_be0 ] f19 o [o] d150v cc ts-pd o[ts-pd] o[ts-pd] ts-pd h[ts-pd] f 1,2 s
lan?sc400 and lansc410 microcontrollers data sheet 57 notes: 1. the shared graphics controller interface and vesa local bus pins: these signals default to three-state with pulldown resistors and remain this way until an lcd or vl-bus interface is selected (all except lvee and lvdd ). when the graphics controller is enabled on the lansc400 microcontroller, the signals will be three-state with pulldowns whenever the lcd is not enabled. this allows the lcd to be powered off in any mode, and prevents damage to the lcd by having it powered when the timing of the signals is not correct. in suspend these signals are three-state with pulldowns. the lcd cannot be driven in suspend. when the vesa local bus interface is enabled, the signals will become the inputs and outputs necessary for vl-bus support. in suspend, the signals support leaving the vl device powered on or off (power-down group f). summary: lcd control signals/vesa local bus control signals (all except lvee and lvdd ) have built-in pulldown resistors that are invoked by: Creset invokes pulldowns. Cgraphics controller disabled and vl-bus disabled invokes pulldowns. Cvl-bus enabled and vl interface programmed for power-down in suspend mode invokes pulldowns (power-down group f). Cgraphics controller enabled and lcd enabled. all pins are outputs with no termination. Cgraphics controller enabled and lcd disabled. all pins are three-state with pulldowns. Cvl-bus enabled and not suspend mode. no pulldowns enabled. summary: lvee and lvdd have built-in pullup and pulldown resistors that are invoked by: Creset invokes pullups. Cvl-bus enabled and vl interface programmed for power-down in suspend mode invokes pulldowns in suspend mode (power-down group f). Cgraphics enabled. drive out high in suspend. Cgraphics enabled. both pins are outputs without pullups or pulldowns. Cvl-bus enabled. no pullups or pulldowns in normal operation. 2. the graphics controller signals lcdd7Clcdd0, m, lc, sck, frm, lvee , and lvdd are not supported on the lansc410 microcontroller.
58 lan?sc400 and lansc410 microcontrollers data sheet table 17. pin state tablemiscellaneous signal name [alternate function] pin # type output drive max load (pf) supply reset state normal operation suspend state power down group note 5 v 32kxtal1 y6 vrtc 1 32kxtal2 y4 vrtc 1 acin w12 sti v cc i-pd i-pd i-pd bbatsen v6 a vrtc i i i 1 bl1 y13 sti v cc ii i bl2 w13 sti v cc ii i blo [clk_io] w14 sti[b] b 50 v cc ii i[o] i i[ts-pd] bndscn_en y11 i v cc i-pd i-pd i-pd lf_hs v5 a av cc analog analog analog lf_int y3 a av cc analog analog analog lf_ls w4 a av cc analog analog analog lf_vid w5 a av cc analog analog analog 2 reset y7 sti v cc ii i 1 spkr v7 o b 50 v cc l o ts-pd sus_res/ kbd_row14 y12 sti/sti v cc ii i notes: 1. the 32-khz crystal signals are active in all modes. the reset signal is enabled as an input in all modes to reset the whole chip. the bbatsen signal is active during reset to sense the state of the backup battery. summary: no pullups or pulldowns on these pins. 2. the lf_vid signal is not supported on the lansc410 microcontroller.
lan?sc400 and lansc410 microcontrollers data sheet 59 table 18. pin state tablepower 1 and ground signal name (alternate function) pin # type gnd d4 gnd d5 gnd d6 gnd d7 gnd d8 gnd d9 gnd d10 gnd d12 gnd d11 gnd e4 gnd f4 gnd g4 gnd h4 gnd h8 thermal gnd h9 thermal gnd h10 thermal gnd h11 thermal gnd h12 thermal gnd h13 thermal gnd j4 gnd j8 thermal gnd j9 thermal gnd j10 thermal gnd j11 thermal gnd j12 thermal gnd j13 thermal gnd k8 thermal gnd k9 thermal gnd k10 thermal gnd k11 thermal gnd k12 thermal gnd k13 thermal gnd l8 thermal gnd l9 thermal gnd l10 thermal gnd l11 thermal gnd l12 thermal gnd l13 thermal gnd m8 thermal gnd m9 thermal gnd m10 thermal gnd m11 thermal gnd m12 thermal
60 lan?sc400 and lansc410 microcontrollers data sheet gnd m13 thermal gnd n8 thermal gnd n9 thermal gnd n10 thermal gnd n11 thermal gnd n12 thermal gnd n13 thermal gnd r17 gnd t17 gnd u5 gnd u6 gnd u7 gnd u8 gnd u9 gnd u10 gnd u11 gnd u12 gnd u13 gnd u14 gnd u15 gnd u16 gnd u17 gnd_a y5 analog v cc a8 i/o v cc a13 i/o v cc a18 i/o v cc b1 i/o v cc b4 i/o v cc b16 i/o v cc e1 i/o v cc e17 i/o v cc g17 i/o v cc h1 i/o v cc j17 i/o v cc j3 i/o v cc l17 logic v cc m1 i/o v cc m17 logic v cc m19 i/o v cc n17 logic v cc p17 logic v cc p18 i/o v cc t1 i/o v cc u18 i/o table 18. pin state tablepower 1 and ground (continued) signal name (alternate function) pin # type
lan?sc400 and lansc410 microcontrollers data sheet 61 v cc v13 i/o v cc _rtc w7 rtc v cc w9 i/o v cc y1 i/o v cc y16 i/o v cc _a w6 analog v cc _cpu k4 cpu v cc _cpu l4 cpu v cc _cpu m4 cpu v cc _cpu n4 cpu v cc _cpu p4 cpu v cc _cpu r4 cpu v cc _cpu t4 cpu notes: 1. see the signal descriptions under the reset and power subheading in the signal description table beginning on page 62 for additional information about the v cc pins. table 18. pin state tablepower 1 and ground (continued) signal name (alternate function) pin # type
62 lan?sc400 and lansc410 microcontrollers data sheet signal descriptions the descriptions in table 19 are organized in alphabetical order within the functional group listed here. n system interface on page 62 n configuration pins on page 63 n memory interface on page 64 n vl-bus interface on page 64 n power management on page 65 n clocks on page 66 n parallel port on page 66 n serial port on page 66 n keyboard interfaces on page 67 n general-purpose input/output on page 67 n serial infrared port on page 67 n pc card controller (lansc400 microcontroller only) on page 67 n lcd graphics controller (lansc400 microcontrol- ler only) on page 68 n boundary scan test interface on page 69 n reset and power on page 69 table 19. signal description table signal type description system interface aen o dma address enable indicates that the current address active on the sa25Csa0 address bus is a memory address, and that the current cycle is a dma cycle. all i/o devices should use this signal in decoding their i/o addresses, and should not respond when this signal is asserted. when aen is asserted, the pdack1 C pdack0 signals are used to select the appropriate i/o device for the dma transfer. aen is also asserted when a dma cycle is occurring internal to the chip. on the lansc400 microcontroller, aen is also asserted for all accesses to the pc card i/o space to prevent isa devices from responding to the ior /iow signal assertions because these signals are shared between the pc card and isa interfaces. bale o bus address latch enable is driven at the beginning of an isa bus cycle with a valid address. this signal can be used by external devices to latch the address for the current cycle. bale is also asserted for all accesses to the pc card interfaces (memory or i/o) (lansc400 microcontroller only) and all dma cycles. this prevents an isa device from responding to a cycle based on a previously latched address. dbufoe o data buffer output enable controls the output enable on the external transceiver required to drive the peripheral data bus in local bus and 32-bit dram modes. dbufrdh o high byte data buffer direction control controls direction of data flow through the external transceiver required to drive the peripheral data bus in local bus and 32-bit dram mode. this is the control signal for the upper 8 bits of the data bus. dbufrdl o low byte data buffer direction control controls direction of data flow through the external transceiver required to drive the peripheral data bus in local bus and 32-bit dram mode. this is the control signal for the lower 8 bits of the data bus. iochrdy sti pu i/o channel ready should be driven by open-drain devices. when pulled low during an isa access, wait states are inserted in the current cycle. this pin has an internal weak pullup that should be supplemented by a stronger external pullup (usually 4.7 k w to 1 k w ) for faster rise time. iocs16 i i/o chip select 16: the targeted i/o device drives this signal active early in the cycle to request a 16-bit transfer. ior o i/o read command indicates that the current cycle is a read from the currently addressed i/o device. when this signal is asserted, the selected i/o device can drive data onto the data bus. this signal is also shared with the pc card interface on the lansc400 microcontroller. iow o i/o write command indicates that the current cycle is a write to the currently addressed i/o device. when this signal is asserted, the selected i/o device can latch data from the data bus. this signal is also shared with the pc card interface on the lansc400 microcontroller. mcs16 i memory chip select 16 indicates to the isa control logic that the targeted memory device is a 16-bit-wide device.
lan?sc400 and lansc410 microcontrollers data sheet 63 memr o memory read command indicates that the current cycle is a read of the currently addressed memory device. when this signal is asserted, the memory device can drive data onto the data bus. memw o memory write command indicates that the current cycle is a write of the currently addressed memory device. when this signal is asserted, the memory device can latch data from the data bus. pdack1 Cpdack0 o programmable dma acknowledge signals can each be mapped to one of the seven available dma channels. they are driven active (low) back to the dma initiator to acknowledge the corresponding dma requests. pdrq1Cpdrq0 i programmable dma requests can each be mapped to one of the seven available dma channels. they are asserted active (high) by a dma initiator to request dma service from the dma controller. pirq7Cpirq0 i programmable interrupt requests can each be mapped to one of the available 8259 interrupt channels. they are asserted when a peripheral requires interrupt service. (rising edge/active high trigger) rstdrv o system reset is the isa bus reset signal. when this signal is asserted, all connected devices reinitialize to their reset state. this signal should not be confused with the internal cpu reset and sreset signals. sa25Csa0 o system address bus outputs the physical memory or i/o port latched addresses. it is used by all external peripheral devices other than main system dram. in addition, this is the local address bus in local bus mode. sbhe o system byte high enable is driven active when the high data byte is to be transferred on the upper 8 bits of the isa data bus. sd15Csd0 b system data bus is shared between isa, 8- or 16-bit rom/flash memory, and pc card peripherals (on the lansc400 microcontroller only) and can be directly connected to all of these devices. in addition, these signals are the upper word of the local data bus, the 32-bit dram interface, and the 32-bit rom interface. in these modes, the system data bus can be generated via an external buffer connected to the sd bus and controlled by the buffer control signals provided. spkr o speaker, digital audio output controls an external speaker driver. it is generated from the internal 8254-compatible timer channel 2 output anded with i/o port 0061h[1] (speaker data enable); on the lansc400 microcontroller, the pc card speaker signals are exclusively ored with each other and the speaker control function of the timer to generate the spkr signal. tc o terminal count is driven from the dma controller pair to indicate that the transfer count for the currently active dma channel has reached zero, and that the current dma cycle is the last transfer. configuration pins bndscn_en i boundary scan enable enables the boundary scan pin functions. when this pin is high, the boundary scan interface is enabled. when this pin is low, the boundary scan pin functions are disabled and the pins are configured to their default functions. this pin must be held low during reset for normal operation. cfg1Ccfg0 i configuration pins 1C0 select the data bus width for the physical device(s) selected by the romc s0 pin (i.e., 8-, 16-, or 32-bit-wide). these pins are sampled at the deassertion of reset . cfg2 i configuration pin 2 selects whether or not the system will boot from pc card socket a memory card or from the device attached to romcs0 . this pin is sampled at the deassertion of reset . this pin is not supported on the lansc410 microcontroller. cfg3 i configuration pin 3 enables the sd buffer control signals, dbufoe , dbufrdh , and dbufrdl . this pin is sampled at the deassertion of reset . table 19. signal description table (continued) signal type description
64 lan?sc400 and lansc410 microcontrollers data sheet memory interface cash3 Ccash0 o column address strobe high indicates to the dram devices that a valid column address is asserted on the ma lines. these cas signals are for the odd banks (banks 1 and 3); cash3 Ccash2 are for the high word; and cash1 Ccash0 is for the low word. casl3 Ccasl0 o column address strobe low indicates to the dram devices that a valid column address is asserted on the ma lines. these cas signals are for the even banks (banks 0 and 2); casl1 Ccasl0 are for the low word; casl3 Ccasl2 are for the high word. d31Cd0 b data bus is used for dram and local bus cycles. this bus is also used when interfacing to 32-bit roms. ma12Cma0 o memory address: the dram row and column addresses are multiplexed onto this bus. row addresses are driven onto this bus and are valid upon the falling edge of ras . column addresses are driven onto this bus and are valid upon the falling edge of cas . mwe o write enable indicates an active write cycle to the dram devices. this signal is also used to three-state edo drams at the end of edo read cycles. r32bfoe o rom 32-bit buffer output enable provides the buffer enable signal for the external transceivers on the low word of the rom interface. this signal is automatically provided when the romcs0 interface is configured as 32 bit (the configuration can be done using either cfg1Ccfg0 or csc index 20h[1C0]). once romcs0 is configured as 32 bit, all accesses to 32-bit rom devices on romcs2 Cromcs0 result in the assertion of the r32bfoe signal. ras3 Cras0 o row address strobe indicates to the dram devices that a valid row address is asserted on the ma lines. romcs2 Cromcs0 o rom chip selects are active low outputs that provide the chip select for the bios rom and/or the rom/flash memory array. after power-on reset, the romcs0 chip select will go active for accesses into the 64-kbyte segment that contains the boot vector, at address 3ff0000h to 3ffffffh. romcs0 can be driven active during a linear (direct) address decode of certain addresses in the high memory (00a0000hC00fffffh) region. by default, direct-mapped accesses to the 64-kbyte region from 00ffff0h to 00fffffh are enabled to support legacy pc/at bios. this area is known as the aliased boot vector. it can also be activated by accessing a memory management system (mms) page that points to the rom0 address space. romcs1 is activated only when accessing an mms page that points to it. a third, mms-mappable romcs2 signal is available by reconfiguring one of the chips general purpose input output (gpio) pins for this function and also requires the use of mms to access devices connected to it. romrd o rom read indicates that the current cycle is a read of the currently selected rom device. when this signal is asserted, the selected rom device can drive data onto the data bus. romwr o rom write indicates that the current cycle is a write of the currently selected rom device. when this signal is asserted, the selected rom device can latch data from the data bus. vl-bus interface vl_ads o local bus address strobe is asserted to indicate the start of a vl-bus cycle. it is always strobed low for one clock period. the address and status lines are valid on the rising edge of vl_lclk, which samples this signal low. vl_be3 Cvl_be0 o local bus byte enables indicate which byte lanes of the 32-bit data bus are involved with the current vl-bus transfer. vl_blast o local bus burst last is asserted to indicate that the next vl_brdy assertion will terminate the current vl-bus transfer. table 19. signal description table (continued) signal type description
lan?sc400 and lansc410 microcontrollers data sheet 65 vl_brdy i local bus burst ready is asserted by the vl-bus target to indicate that it is terminating the current burst transfer. the chip samples this signal on the rising edge of vl_lclk. vl_brdy should be asserted for one vl_lclk period per burst transfer. if vl_lrdy is asserted at the same time as vl_brdy , vl_brdy is ignored and the vl-bus transfer is terminated. vl_d/c vl_m/io vl_w/r o o o local bus data/code status is driven low to indicate that code is being transferred. a high on this signal indicates that data is being transferred. local bus memory/i/o status is driven low to indicate an i/o transfer. a high on this signal indicates a memory transfer. local bus write/read status is driven low to indicate a read transfer. a high on this signal indicates a write. vl_lclk o local bus clock is the vl-bus clock. it is used by the vl-bus target for all timing references. this signal is in phase with the internal cpus clock input. (rising edge active) vl_ldev i local bus device select is asserted by the vl-bus target to indicate that it is accepting the current transfer as indicated by the address and status lines. the vl-bus target asserts this signal as a function of the address and status presented on the bus. vl_lrdy i local bus ready is asserted by the vl-bus target to indicate that it is terminating the current bus cycle. this signal is sampled by the chip on the rising edge of vl_lclk. vl_rst o local bus reset is the vl-bus master reset. it is controlled with csc index 14h[4]. power management acin i ac supply active indicates to the system that it is being powered from an ac source. when asserted, this signal can disable power management functions (if configured to do so). bl2 Cbl0 i battery low detects indicate to the chip the current status of the systems primary battery pack. bl0 Cbl2 can indicate various conditions of the battery as conditions change. these inputs can be used to force the system into one of the power saving modes when activated (low-going edge). lbl2 o latched battery low detect 2 can be driven low and latched on the low-going edge of the bl2 input to indicate to the system that the chip has been forced into the suspend mode by a battery dead indication from the bl2 signal. it is cleared by one of the all clear indicators that allow the system to resume after a battery dead indication. sus_res i suspend/resume operation: when the chip is in hyper-speed, high-speed, low-speed, or standby mode, a software-configurable edge on this pin can cause the internal logic to enter suspend mode. when in suspend, a software-configurable edge on this pin can cause the chip to enter the high-speed or low-speed mode. the choice of edge is configured using the sus_res pin configuration register at csc index 50h. table 19. signal description table (continued) signal type description bus cycle initiated vl_m/io vl_d/c vl_w/r interrupt acknowledge 0 0 0 halt/special cycle 0 0 1 i/o read 0 1 0 i/o write 0 1 1 code read 1 0 0 reserved 1 0 1 memory read 1 1 0 memory write 1 1 1
66 lan?sc400 and lansc410 microcontrollers data sheet clocks 32kxtal1 32kxtal2 32.768-khz crystal interface signals are used for the 32.768-khz crystal. this is the main clock source for the chip and drives the internal phase-locked loops (plls) that generate all other clock frequencies needed in the system. clk_io i/o clock input/output is an input to drive the integrated 8254 timer with a 1.19318-mhz clock signal from an external source, or an output to bring out certain internal clock sources to drive external devices. lf_int, lf_ls, lf_vid, lf_hs a loop filters connect external rc loop filters required by the internal plls. lf_vid is not supported on the lansc410 microcontroller. parallel port (note: the names in parentheses in this section are those used in epp mode.) ack (intr) i printer acknowledge: in standard mode, this signal is driven by the parallel port device with the state of the printer acknowledge signal. in epp mode, this signal indicates to the chip that the parallel port device has generated an interrupt request. afdt (dstrb )o auto line feed detect: in standard mode, this signal is driven by the chip indicating to the parallel port device to insert a line feed at the end of every line. in epp mode, this signal is driven active by the chip during reads or writes to the epp data registers. busy (wait )i printer busy: in standard mode, this signal is driven by the parallel port device with the state of the printer busy signal. in epp mode, this signal adds wait states to the current cycle. error i error: the printer asserts this signal to inform the parallel port of a deselect condition, paper end (pe) or other error condition. init o initialize printer: this signals the printer to begin an initialization routine. pe i paper end: the printer asserts this signal when it is out of paper. ppdwe o parallel port write enable controls an external 374 type latch in a unidirectional parallel port design. this device latches the sd7Csd0 bus onto the parallel port data bus. to implement a bidirectional parallel port, this pin can be reconfigured to act as an address decode for the parallel port data port. ppdwe can then be externally gated with ior and iow to provide the parallel port data read and write strobes, respectively. ppoen o parallel port output buffer enable supports a bidirectional parallel port design. ppoen controls the output enable of the external parallel port output buffer (373 octal d-type transparent latch). slct i printer select is returned by a printer upon receipt of slctin . slctin (astrb )o printer selected: in standard mode, this signal is driven by the chip to select the parallel port device. in epp mode, this signal is driven active by the chip during reads or writes to the epp address register. strb (write )o strobe: in standard mode, this signal indicates to the parallel port device to latch the data on the parallel port data bus. in epp mode, this signal is driven active during writes to the epp data or the epp address register. serial port cts i clear to send is driven back to the serial port to indicate that the external data carrier equipment (dce) is ready to accept data. dcd i data carrier detect is driven back to the serial port from a piece of data carrier equipment when it has detected a carrier signal from a communications target. dsr i data set ready indicates that the external dce is ready to establish a communication link with the internal serial port controller. dtr o data terminal ready indicates to the external dce that the internal serial port controller is ready to communicate. rin i ring indicate is used by an external modem to inform the serial port that a ring signal was detected. a change in state on this signal by the external modem can be configured to cause a modem status interrupt. this signal can be used to cause the chip to resume from a suspend state. table 19. signal description table (continued) signal type description
lan?sc400 and lansc410 microcontrollers data sheet 67 rts o request to send indicates to the external dce that the internal serial port controller is ready to send data. sin i serial data in receives the serial data from the external serial device or dce into the internal serial port controller. sout o serial data out transmits the serial data from the internal serial port controller to the external serial device or dce. keyboard interfaces kbd_col7C kbd_col0 o matrix-scanned keyboard column outputs drive the matrix keyboard column lines. (open collector output with programmable termination) kbd_row14C kbd_row0 sti matrix-scanned keyboard row inputs samples the row lines on the matrix keyboard. xt_clk i/o xt keyboard clock is the clock signal for an external xt keyboard interface. (open collector output) xt_data i/o xt keyboard data is the data signal for an external xt keyboard interface. (open collector output) general-purpose input/output gpio31Cgpio15 gpio_cs14C gpio_cs0 b general purpose i/os and programmable chip selects each of the gpios can be programmed to be an input or an output. as outputs, all of the gpios can be programmed to be high or low. some of the gpios can be programmed to be high or low for each of the power management modes. also as outputs, some of these pins can be individually programmed as chip selects for other external peripheral devices. these can be configured as direct memory address decodes or i/o decodes qualified or non-qualified by the isa bus command signals. any one of the gpio_csx signals can be configured as romcs2 . as inputs, all the gpios can be read back with a register bit. some of these pins can be individually programmed to act as activity triggers, wake-up sources, or smis. serial infrared port sirin i infrared serial input is the digital input for the serial infrared interface. sirout o infrared serial output is the digital output for the serial infrared interface. pc card controller (lansc400 microcontroller only) (note: the names in parentheses in this section are those used in pc card memory and i/o mode.) bvd1_a (stschg_a )C bvd1_b (stschg_b ) i battery voltage detect is driven low by a pc card when its on-board battery is dead. when the pc card interface is configured for i/o, this signal can be driven by the card to indicate a card status change. it is typically used to generate a system irq in this mode. these signals are not supported on the lansc410 microcontroller. bvd2_a (spkr_a ) (drq_a)C bvd2_b (spkr_b ) (drq_b) i battery voltage detect is driven low by a pc card when its on-board battery is weak. when the pc card interface is configured for i/o, this signal can be driven by the cards speaker output. when enabled, this signal can drive the chip spkr output. when pc card dma is enabled, the dma request from the pc card can be programmed to appear on this signal. see also the description for wp_a (iois16_a ) (drq_a) and wp_b (iois16_b ) (drq_b); the dma request can also be programmed to appear on these pins. these signals are not supported on the lansc410 microcontroller. cd_a Ccd_b cd_a2 i card detect indicates that the card is properly inserted. socket a is capable of being configured to use two card detect inputs and socket b is only provided with one. if only one card detect is to be used for a socket, the input signals should be driven from a logical and (digital or) of the cd1 and cd2 signals from their respective card interfaces. these signals are not supported on the lansc410 microcontroller. table 19. signal description table (continued) signal type description
68 lan?sc400 and lansc410 microcontrollers data sheet icdir o card data direction controls the direction of the card data buffers or voltage translators. it works with the mcel and mceh card enable signals to control data buffers on the card interface. when this signal is high, the data flow is from the chip to the card socket, indicating a data write cycle. when this signal is low, the data flow is from the card socket into the chip, indicating a read cycle. this signal is not supported on the lansc410 microcontroller. mceh_a , mceh_b o card enables, high byte enables a pc cards high data bus byte transceivers for the respective card interfaces. these signals are not supported on the lansc410 microcontroller. mcel_a , mcel_b o card enables, low byte enables a pc cards low data bus byte transceivers for the respective card interfaces. these signals are not supported on the lansc410 microcontroller. oe o pc card output enable: this is the pc card memory read signal. this signal is not supported on the lansc410 microcontroller. pcma_vcc o pc card socket a v cc enable can be used to control the v cc to socket a. this signal is not supported on the lansc410 microcontroller. pcma_vpp2C pcma_vpp1 o pc card socket a vpp selects can be used to control the v pp to socket a. these signals are not supported on the lansc410 microcontroller. pcmb_vcc o pc card socket b v cc enable can be used to control the v cc to socket b. this signal is not supported on the lansc410 microcontroller. pcmb_vpp2C pcmb_vpp1 o pc card socket b vpp selects can be used to control the v pp to socket b. these signals are not supported on the lansc410 microcontroller. rdy_a (ireq_a ), rdy_b (ireq_b ) i card ready indicates that the respective card is ready to accept a new data transfer command. when the card interface is configured as an i/o interface, this signal is used as the card interrupt request input into the chip. these signals are not supported on the lansc410 microcontroller. reg_a (dack_a), reg_b (dack_b) o attribute memory select signals are driven inactive (high) for accesses to a pc cards common memory, and asserted (low) for accesses to a pc cards attribute memory and i/o space for their respective card interfaces. when pc card dma is enabled, the dma acknowledge to the pc card appears on this signal. these signals are not supported on the lansc410 microcontroller. rst_a, rst_b o card reset signals are the reset for their respective cards. when active, this signal clears the interrupt and general control register (pc card index 03h and 43h), thus placing a card in an unconfigured (memory-only mode) state. it also indicates the beginning of any additional card initialization. these signals are not supported on the lansc410 microcontroller. wait_ab i extend bus cycle delays the completion of the memory access or i/o access that is currently in progress. when this signal is asserted (low), wait states are inserted into the cycle in progress. only one wait input is provided on the chip. external logic is required for a two-socket implementation to logically and (digitally or) each cards wait signal together. this signal is not supported on the lansc410 microcontroller. we (tc) o pc card write enable is the pc card memory write signal. data is transferred from the chip to the pc card. when pc card dma is enabled, the dma terminal count to the pc card appears on this signal. this signal is not supported on the lansc410 microcontroller. wp_a (iois16_a ) (drq_a), wp_b (iois16_b ) (drq_b) i write protect indicates the status of the respective cards write protect switch. when the respective card is configured for an i/o interface, this signal is used by the card to indicate back to the chip that the currently accessed port is 16 bits wide. when pc card dma is enabled, the dma request from the pc card can be programmed to appear on this signal. see also the description for bvd2_a (spkr_a ) (drq_a) and bvd2_b (spkr_b ) (drq_b); the dma request can also be programmed to appear on these pins. these signals are not supported on the lansc410 microcontroller. lcd graphics controller (lansc400 microcontroller only) frm o lcd panel line frame start is asserted by the chip at the start of every frame to indicate to the lcd panel that the next data clocked out is intended for the start of the first scan line on the panel. some panels refer to this signal as flm or s (scan start-up). this signal is not supported on the lansc410 microcontroller. table 19. signal description table (continued) signal type description
lan?sc400 and lansc410 microcontrollers data sheet 69 lc o lcd panel line clock is activated at the start of every pixel line. it is commonly referred to by lcd data sheets as cl1 or cp1. this signal is not supported on the lansc410 microcontroller. lcdd7Clcdd0 o lcd panel data bits: lcdd7Clcdd0 are data bits for the lcd panel interface. when driving 4-bit single-scan panels, bits 3C0 form a nibble-wide lcd data interface. in dual-scan panel mode, lcdd3Clcdd0 are the data bits for the top half of the lcd, and lcdd7C lcdd4 are the data bits for the bottom half of the lcd. when driving 8-bit single-scan panels (monochrome or color stn), these bits are the 8-bit data interface. these signals are not supported on the lansc410 microcontroller. lvdd o lcd panel vdd voltage control is used to control the assertion of the lcds v dd voltage. this is provided to be part of the solution in sequencing the panels v dd , data, and v ee in the proper order during panel power-up and power-down to prevent damage to the panel from cmos driver latch up. v dd is used to power the lcd logic and is usually +5 v or +3 v dc. this signal is not supported on the lansc410 microcontroller. lvee o lcd panel vee voltage control is used to control the assertion of the lcds v ee voltage. this is provided to be part of the solution in sequencing the panels v dd , data, and v ee in the proper order during panel power-up and power-down to prevent damage to the panel from cmos driver latch up. v ee is the lcd contrast voltage and is either positive or negative with an amplitude of 15C30 v dc.this signal is not supported on the lansc410 microcontroller. mo lcd panel ac modulation is the ac modulation signal for the lcd. ac modulation causes the lcd panel drivers to reverse polarity to prevent an internal dc bias from forming on the panel. this signal is not supported on the lansc410 microcontroller. sck o lcd panel shift clock is the nibble/byte strobe used by the lcd panel to latch a nibble or byte of incoming data. commonly referred to by lcd panels as cl2 or cp2. this signal is not supported on the lansc410 microcontroller. boundary scan test interface bndscn_tck i test clock is the boundary-scan input clock that is used to shift serial data patterns in from bndscn_tdi. bndscn_tdi i test data input is the serial input stream for boundary-scan input data. this pin has a weak internal pullup resistor. it is sampled on the rising edge of bndscn_tck. if not driven, this input is sampled high internally. bndscn_tdo o ts test data output is the serial output stream for boundary-scan result data. it is in the high- impedance state except when scanning is in progress. bndscn_tms i test mode select is an input for controlling the test access port. this pin has a weak internal pullup resistor. if it is not driven, it is sampled high internally. reset and power bbatsen a backup battery sense: rtc (real time clock) backup battery voltage is sampled on this pin each time the av cc pin has power applied to it followed by a chip master reset. if this samples below 2.4 v, the vrt bit (rtc index 0dh) is cleared until read one time. at this time, the vrt bit is set until bbatsen is sampled again. bbatsen also provides a power-on- reset signal for the rtc when an rtc backup battery is applied for the first time. gnd ground pins reset i reset input is an asynchronous hardware reset input equivalent to powergood in the at system architecture. v cc 3.3-v dc supply pins provide power to the discrete logic and i/o pins. v cc _a analog 3.3-v supply pins provide power to the analog section of the chip, including the internal plls and integrated oscillator circuit. extreme care should be taken that this supply voltage is isolated properly to provide a clean, noise free voltage to the plls. v cc _cpu cpu 3.3-v dc supply pins provide power to the internal cpu. v cc _rtc rtc 3.3-v supply pin provides power to the internal real-time clock and on-board static/ configuration ram. this pin can be driven independently of all other power pins. table 19. signal description table (continued) signal type description
70 lan?sc400 and lansc410 microcontrollers data sheet multiplexed pin function options table 20 shows how to configure each multiplexed signal on the lansc400 and lansc410 microcontrollers. note that those signals marked with a superscript 1 ( 1 ) are not supported on the lansc410 microcontroller. pins with multiplexed functions have their functions selected in one of three ways: n by configuration pins that are latched during reset n by assertion at bndscn_en n by firmware via programmed configuration registers table 20. multiplexed pin configuration options signal you want signals you give up how to configure the signal you want on the pin pin # system interface bale kbd_row10 set csc index 39h[2]. d2 dbufoe gpio_cs4 hardwire strap the cfg3 pin high. c4 dbufrdh gpio_cs3 hardwire strap the cfg3 pin high. d17 dbufrdl gpio_cs2 hardwire strap the cfg3 pin high. c18 mcs16 kbd_row12 set csc index 39h[2]. f3 pdack1 kbd_row7 set csc index 39h[2]. d3 pdrq1 kbd_row8 set csc index 39h[2]. c2 pirq0 gpio_cs8 set csc index 38h[1]. w18 pirq1 gpio_cs7 set csc index 38h[2]. y19 pirq2 kbd_row9 set csc index 39h[2]. e3 pirq3 kbd_col2 set csc index 3ah[1]. a2 pirq4 kbd_col3 set csc index 3ah[1]. b3 pirq5 kbd_col4 set csc index 3ah[2]. c3 pirq6 kbd_col5 set csc index 3ah[2]. a1 pirq7 kbd_col6 set csc index 3ah[2]. b2 r32bfoe kbd_row13 hardwire-strap both the cfg1 and cfg0 pins high to enable the 32-bit rom interface on romsc0 . this automatically enables r32bfoe . a3 sbhe kbd_row11 set csc index 39h[2]. c1 configuration pins (pinstraps) (see using the configuration pins to select pin functions on page 74.) memory interface cash2 kbd_row2 set bit 3 of the dram bank x configuration register. set csc index 00h[7] and 00h[3], or set csc index 01h[7] and 01h[3], or set csc index 02h[7], or set csc index 03h[7]. c17 cash3 kbd_row3 b18 casl2 kbd_row0 b19 casl3 kbd_row1 d16 ma12 kbd_row6 b17 ras2 kbd_row4 d15 ras3 kbd_row5 c16
lan?sc400 and lansc410 microcontrollers data sheet 71 vl-bus interface vl_ads lcdd1 1 enable the vl-bus interface by setting csc index 14h[3]. c19 vl_be0 sck 1 f19 vl_be1 lc 1 e20 vl_be2 m 1 f18 vl_be3 lcdd7 1 d20 vl_blast lvdd 1 a19 vl_brdy lvee 1 a20 vl_d/c lcdd5 1 e18 vl_lclk frm 1 e19 vl_ldev lcdd6 1 f17 vl_lrdy lcdd4 1 d19 vl_m/io lcdd3 1 c20 vl_rst lcdd0 1 b20 vl_w/r lcdd2 1 d18 isa bus aen gpio_cs10 set csc index 38h[0]. v17 iochrdy gpio_cs6 set csc index 38h[3]. v18 iocs16 gpio_cs5 set csc index 38h[4]. w19 pdack0 gpio_cs11 set csc index 38h[0] w17 pdrq0 gpio_cs12 set csc index 38h[0]. y17 tc gpio_cs9 set csc index 38h[0]. y18 gpios gpio15 pcma_vpp2 1 clear csc index 39h[5]. y15 gpio16 pcmb_vcc 1 clear csc index 39h[6]. v15 gpio17 pcmb_vpp1 1 clear csc index 39h[6]. w15 gpio18 pcmb_vpp2 1 clear csc index 39h[6]. y14 gpio19 lbl2 clear csc index 39h[4]. v14 gpio20 cd_a2 1 clear csc index 3ah[0]. g18 gpio21 ppdwe clear csc index 39h[1C0]. v3 gpio22 ppoen clear csc index 39h[1C0]. t3 gpio23 slct, wp_b 1 clear csc index 39h[1C0]. u4 gpio24 busy, bvd2_b 1 clear csc index 39h[1C0]. u3 gpio25 ack , bvd1_b 1 clear csc index 39h[1C0]. u2 gpio26 pe, rdy_b 1 clear csc index 39h[1C0]. w2 gpio27 error , cd_b 1 clear csc index 39h[1C0]. v4 gpio28 init , reg_b 1 clear csc index 39h[1C0]. y2 gpio29 slctin , rst_b 1 clear csc index 39h[1C0]. w3 gpio30 afdt , mceh_b 1 clear csc index 39h[1C0]. w1 gpio31 strb , mcel_b 1 clear csc index 39h[1C0]. v2 gpio_cs2 dbufrdl hardwire-strap the cfg3 pin low. c18 gpio_cs3 dbufrdh hardwire-strap the cfg3 pin low. d17 gpio_cs4 dbufoe hardwire-strap the cfg3 pin low. c4 gpio_cs5 iocs16 clear csc index 38h[4]. w19 gpio_cs6 iochrdy clear csc index 38h[3]. v18 gpio_cs7 pirq1 clear csc index 38h[2]. y19 gpio_cs8 pirq0 clear csc index 38h[1]. w18 gpio_cs9 tc clear csc index 38h[0]. y18 gpio_cs10 aen clear csc index 38h[0]. v17 table 20. multiplexed pin configuration options (continued) signal you want signals you give up how to configure the signal you want on the pin pin #
72 lan?sc400 and lansc410 microcontrollers data sheet gpio_cs11 pdack0 clear csc index 38h[0]. w17 gpio_cs12 pdrq0 clear csc index 38h[0]. y17 gpio_cs13 pcma_vcc 1 clear csc index 39h[5]. v16 gpio_cs14 pcma_vpp1 1 clear csc index 39h[5]. w16 parallel port ack gpio25, bvd1_b 1 write csc index 39h[1C0] to 10. u2 afdt gpio30, mceh_b 1 w1 busy gpio24, bvd2_b 1 u3 error gpio27, cd_b 1 v4 init gpio28, reg_b 1 y2 pe gpio26, rdy_ b 1 w2 ppdwe gpio21 v3 ppoen gpio22 t3 slct gpio23, wp_b 1 u4 slctin gpio29, rst_b 1 w3 strb gpio31, mcel_b 1 v2 keyboard interface kbd_col0 xt_data clear csc index 39h[3]. e2 kbd_col1 xt_clk clear csc index 39h[3]. d1 kbd_col2 pirq3 clear csc index 3ah[1]. a2 kbd_col3 pirq4 clear csc index 3ah[1]. b3 kbd_col4 pirq5 clear csc index 3ah[1]. c3 kbd_col5 pirq6 clear csc index 3ah[1]. a1 kbd_col6 pirq7 clear csc index 3ah[1]. b2 kbd_row0 casl2 clear csc index 00h[7] and 00h[3], or clear csc index 01h[7] and 01h[3], or clear csc index 02h[7], or clear csc index 03h[7]. b19 kbd_row1 casl3 d16 kbd_row2 cash2 c17 kbd_row3 cash3 b18 kbd_row4 ras2 d15 kbd_row5 ras3 c16 kbd_row6 ma12 b17 kbd_row7 pdack1 clear csc index 39h[2]. d3 kbd_row8 pdrq1 clear csc index 39h[2]. c2 kbd_row9 pirq2 clear csc index 39h[2]. e3 kbd_row10 bale clear csc index 39h[2]. d2 kbd_row11 sbhe clear csc index 39h[2]. c1 kbd_row12 mcs16 clear csc index 39h[2]. f3 kbd_row13 r32bfoe do not enable the 32-bit rom interface on romcs0 (e.g., do not hardwire-strap both the cfg1 and cfg0 pins high). a3 xt_clk kbd_col1 clear csc index 39h[3]. d1 xt_data kbd_col0 clear csc index 39h[3]. e2 pc card (lansc400 microcontroller only) bvd1_b 1 gpio25, ack write csc index 39h[1C0] to 01. u2 bvd2_b 1 gpio24, busy write csc index 39h[1C0] to 01. u3 cd_a2 1 gpio20 set csc index 3ah[0]. g18 cd_b 1 gpio27, error write csc index 39h[1C0] to 01. v4 lbl2 1 gpio19 set csc index 39h[4]. v14 mceh_a 1 bndscn_tms pull the bndscn_en pin low. n3 mceh_b 1 gpio30, afdt write csc index 39h[1C0] to 01. w1 mcel_a 1 bdnscn_tck pull the bndscn_en pin low. p2 table 20. multiplexed pin configuration options (continued) signal you want signals you give up how to configure the signal you want on the pin pin #
lan?sc400 and lansc410 microcontrollers data sheet 73 mcel_b 1 gpio31, strb write csc index 39h[1C0] to 01. v2 pcma_vcc 1 gpio_cs13 set csc index 39h[5]. v16 pcma_vpp1 1 gpio_cs14 set csc index 39h[5]. w16 pcma_vpp2 1 gpio15 set csc index 39h[5]. y15 pcmb_vcc 1 gpio16 set csc index 39h[6]. v15 pcmb_vpp1 1 gpio17 set csc index 39h[6]. w15 pcmb_vpp2 1 gpio18 set csc index 39h[6]. y14 rdy_b 1 gpio26, pe write csc index 39h[1C0] to 01. w2 reg_a 1 bndscn_tdo pull the bndscn_en pin low. m2 reg_b 1 gpio28, init write csc index 39h[1C0] to 01. y2 rst_a 1 bndscn_tdi pull the bndscn_en pin low. r1 rst_b 1 gpio29, slctin write csc index 39h[1C0] to 01. w3 wp_b 1 gpio23, slct write csc index 39h[1C0] to 01. u4 lcd graphics controller (lansc400 microcontroller only) frm 1 vl_lclk enable the graphics controller by setting csc index ddh[2]. e19 lc 1 vl_be1 e20 lcdd0 1 vl_rst b20 lcdd1 1 vl_ads c19 lcdd2 1 vl_w/r d18 lcdd3 1 vl_m/io c20 lcdd4 1 vl_lrdy d19 lcdd5 1 vl_d/c e18 lcdd6 1 vl_ldev f17 lcdd7 1 vl_ be3 d20 lvdd 1 vl_blast a19 lvee 1 vl_brdy a20 m 1 vl_ be2 f18 sck 1 vl_be0 f19 boundary scan interface bdnscn_tck mcel_a 1 pull the bndscn_en signal high. p2 bndscn_tdi rst_a 1 r1 bndscn_tdo reg_a 1 m2 bndscn_tms mceh_a 1 n3 miscellaneous bl0 clk_io write csc index 38h[7C6] to 01. w14 clk_io bl0 write csc index 38h[7C6] to 10 to enable clk_io as an output or to 11 to enable clk_io as a timer clock input. w14 notes: 1. this signal is not supported on the lansc410 microcontroller. table 20. multiplexed pin configuration options (continued) signal you want signals you give up how to configure the signal you want on the pin pin #
74 lan?sc400 and lansc410 microcontrollers data sheet using the configuration pins to select pin functions the configuration pins are used only for those func- tions that must be selected at reset, prior to firmware execution. all other i/o functions are selected using configuration registers. table 21 provides an overview of the configuration pin functions. all of the cfg pins have weak internal pull- down resistors that select the default function. external pullup resistors are required to select an alternative function. notes: 1. cfg3 is defined as the enable/disable for the dbufoe , dbufrdl , and dbufrdh signals. they can be enabled independently of whether a x32 d bus is selected via the firmware to support the vl local bus or x32 dram interface. 2. the x32 rom option must be selected for romcs0 for the r32bfoe signal to be enabled. the selection of the dbufoe , dbufrdl , and dbufrdh signals are still dependent only on the cfg3 signal. cfg0 and cfg1 pins these pins (shown in table 22) configure the data bus width (x8, x16, or x32) of the rom interface that is se- lected by the romcs0 pin. if a x32 rom is selected, these pins also enable the rom x32 data bus buffer output enable signal (r32bfoe ). if a 32-bit data bus width is selected for the rom interface, the r32bfoe signal will be asserted for all romcsx accesses to 32-bit rom. exercise caution because the data bus width for the romcs0 interface can also be changed through programming. this feature was implemented mainly for testing. . cfg2 pinlansc400 microcontroller only this configuration pin (see table 23) is used on the lansc400 microcontroller to select the romcs0 steering at system boot time. the boot rom chip se- lect (romcs0 ) can either be enabled to drive the romcs0 pin or can be rerouted to drive the pc card (socket a only) interface chip selects. the cfg0 and cfg1 pins are still used to select the data bus width for the romcs0 decode, regardless of the cfg2 config- uration. the pc card romcs0 redirection should not be selected when the cfg0 and cfg1 configuration pins are set to select a x32 rom interface. when the rom chip select decode has been redi- rected to pc card socket a, all of the normal pc card controller features can still be used to drive the pc card socket a interface. the rom chip select decode remapping to the pc card socket can be enabled and disabled using firmware at any time. table 21. pinstrap bus buffer options cfg3 ( 1 ) cfg1 cfg0 romcs0 data width dbufoe dbufrdl dbufrdh r32bfoe 0 0 0 x8 disabled disabled 0 0 1 reserved reserved reserved 0 1 0 x16 disabled disabled 011x32 2 disabled enabled 1 0 0 x8 enabled disabled 1 0 1 reserved reserved reserved 1 1 0 x16 enabled disabled 111x32 2 enabled enabled table 22. cfg0 and cfg1 configuration cfg1 cfg0 configuration 00x8 romcs0 rom interface 01reserved 1 0 x16 romcs0 rom interface 1 1 x32 romcs0 rom interface table 23. cfg2 configuration (lansc400 microcontroller only) cfg2 configuration 0 enables the romcs0 decode on the romcs0 pin 1 enables the romcs0 decode to access pc card socket a
lan?sc400 and lansc410 microcontrollers data sheet 75 cfg3 pin this configuration pin is used for selecting between the gpio_cs4Cgpio_cs2 i/o pins and the sd bus buffer control signals: dbufoe , dbufrdl , and dbufrdh . when the buffer control signal configuration is selected using the cfg3 pin, the dbufoe , dbufrdl , and dbufrdh signals are driven from boot time on for all accesses to the peripheral data bus. these signals are used for the external system bus transceiver control. see table 24 for the cfg3 configuration definitions. bndscn_en pin the bndscn_en configuration pin (see table 25) is used to enable the boundary scan function i/o pins. the following pins are configured for their boundary scan function when bndscn_en is asserted: n bndscn_tck n bndscn_tms n bndscn_tdi n bndscn_tdo table 24. cfg3 configuration cfg3 configuration 0 enables the gpio_cs4Cgpio_cs2 signals on the i/o pins 1 enables the sd bus buffer control signals dbufoe , dbufrdl , and dbufrdh on the i/o pins table 25. bndscn_en configuration bndscn_en configuration 0 enables the pc card function 1 enables the boundary scan functions: bndscn_tck, bndscn_tms, bndscn_tdi, and bndscn_tdo
76 lan?sc400 and lansc410 microcontrollers data sheet clocking clock generation the lansc400 and lansc410 microcontrollers re- quire only one 32.768-khz crystal to generate all the other clock frequencies required by the system. the output of the on-chip crystal oscillator circuit is used to generate the various frequencies by utilizing four phase-locked loop (pll) circuits. the pll clock dis- tribution scheme is shown in figure 4. table 26 shows all the pll output frequencies and their usage. (note that these four pll circuits are in addition to the inter- nal cpu pll and do not replace it.) the crystal oscillator needs two pins, but it does not re- quire any external components except the crystal; the load capacitors and the feedback resistor are inte- grated on-chip. the four plls are called intermediate pll, low-speed pll, high-speed pll, and graphics dot clock pll. each of the integrated phase-locked loops has a dedi- cated pin to support the required external loop filter. these pins are: lf_int (intermediate pll), lf_ls (low-speed pll), lf_hs (high-speed pll), and lf_vid (graphics dot clock pll). (the lf_vid pin is not supported on the lansc410 microcontroller.) two capacitors and one resistor are required to implement each loop filter. figure 4. clock generation block diagram notes: on the lansc400 microcontroller, the graphics controllers dram interface is clocked by the 66-mhz dram clock. both the rom/flash memory interface and the pc card controller are clocked from the cpu clock. they also have the option to be run from the slow system clock. neither the graphics controller nor the pc card controller are supported on the lansc410 microcontroller. 32.768-khz crystal oscillator intermediate low-speed graphics high-speed 20.736C 36.864 mhz 32.768 khz 66.3552 mhz 1.47456 mhz 36.864 mhz pll pll dot clock pll pll real-time clock pmu uart timer graphics isa bus dram dma cpu and controller controller controller divisors divisors dram controller vl-bus controller rom/flash interface pc card controller
lan?sc400 and lansc410 microcontrollers data sheet 77 integrated peripheral clock sources table 26 and figure 5 show the primary peripheral clocks internal to the microcontroller and the pll and divider sources that are used in the generation of these clocks. note that several of the peripheral clocks are programmable. this programmability is either directly controlled by system firmware or is forced due to a power-management mode change. the graphics con- troller and the pc card controller are not supported on the lansc410 microcontroller. table 26. integrated peripheral clock sources source pll divider resulting frequency where used intermediate pll 1.4746 mhz 1 1.4746 mhz low-speed pll input low-speed pll 36.864 mhz 1 36.864 mhz high-speed pll input graphics dot clock pll input 20 1.8432 mhz uart 2 18.4328 mhz uart 31 1.1892 mhz pit graphics dot clock pll 36.864 mhz programmable 20.736C36.864 mhz graphics controller dot clock 1 36.864 mhz graphics controller high-speed pll 66.3552 mhz 1 66.3552 mhz dram controller graphics controller 2 33.1776 mhz cpu vl-bus controller 4 16.5888 mhz cpu vl-bus controller dma controller 8 8.2944 mhz cpu vl-bus controller isa bus controller rom/flash memory interface dma controller pc card controller 16 4.1472 mhz cpu vl-bus controller isa bus controller rom/flash memory interface dma controller pc card controller 32 2.0736 mhz cpu vl-bus controller isa bus controller rom/flash memory interface dma controller pc card controller 64 1.0368 mhz cpu vl-bus controller isa bus controller rom/flash memory interface dma controller pc card controller
78 lan?sc400 and lansc410 microcontrollers data sheet figure 5. clock source block diagram /4 /8 /16 33.1776 mhz 16.5888 mhz 8.2944 mhz 4.1472 mhz 2.0736 mhz 1.0368 mhz 66.3552 mhz /32 /64 /2 dram clock select cpu clock select isa bus clock select dma clock select 36.864 mhz dram and cpu and isa bus, rom, dma controllers 32.768 khz pll block 1.4746 mhz 36.864 mhz 20.736 mhzC 66.3552 mhz intermediate pll low-speed pll graphics dot high-speed pll oscillator /2 clk_io graphics /20 /31 1.1892 mhz 1.19318 mhz uart 18.432 mhz 1.8432 mhz 32.768 khz rtc clk_io 32.768 khz dot clock timer clock pll 36.864 mhz graphics dot clock select enable enable enable enable pmu clk_io select controllers controller controller dram controller and pmu vl-bus controller graphics and pc card notes: the graphics controller and the pc card controller are not supported on the lansc410 microcontroller.
lan?sc400 and lansc410 microcontrollers data sheet 79 32-khz crystal oscillator the 32-khz oscillator circuit is shown in figure 6; the only external component required for operation is a 32.768-khz crystal. the inverting amplifier (amp) is in- tegrated on-chip together with the feedback resistor and the load capacitors. as shown in figure 7, the on- chip oscillator circuit can be bypassed by removing the external crystal, grounding the 32kxtal1 pin, and driving the 32kxtal2 pin with an external 32-khz clock. (the 32kxtal2 pin should not exceed 2.0 v.) when 32kxtal1 is grounded, the amplifier no longer affects the circuit. figure 6. 32-khz crystal circuit figure 7. 32-khz oscillator circuit loop filters each of the plls in the lansc400 and lansc410 mi- crocontrollers requires an external loop filter. for a cleaner circuit, the designer should consider the following: n place the loop filter components as close as possible to the loop filter signals (lf_int, lf_ls, lf_hs, and lf_vid (lansc400 microcontroller only)), which are located in one corner of the microcontroller. n route the loop filter signals first and by hand. n keep all clocks and noisy signals away from the loop filter area (even on the inner layers). for an even cleaner circuit, the designer could option- ally place an analog v cc power plane directly under the loop filter circuit. the value of the loop filter parameters can also affect the performance of the filter. for example, the values of c1 and r affect lock time and jitter (increasing rc in- creases lock time and decreases jitter). the value of c2 can help clean up high-frequency noise. note that using too large of values for the components can cause the pll to become unstable. the loop filter component value specifications are shown in table 28 on page 84. intermediate and low-speed plls figure 8 on page 80 shows the block diagram for both the intermediate and low-speed plls. each consists of a phase detector, a charge pump, a voltage con- trolled oscillator (vco), an external loop filter, and a feedback divider. this is a generic implementation of the charge-pump pll architecture; all four plls use the same architecture. the intermediate and low- speed plls differ only in component values and fre- quency of operation. the phase detector compares the phase and fre- quency of the two clock signals, reference frequency (fr) and feedback frequency (ff). the up signal is a logic 1 if fr leads ff, while the down signal is a logic 1 if ff leads fr. the up and down signals control the charge pump. the charge pump either charges or dis- charges the loop filter capacitors to change the vco input voltage level. because the vco output frequency tracks the vco input voltage, the vco output fre- quency is adjusted whenever fr and ff differ in phase or frequency. the feedback divide ratio determines the frequency multiplication factor. frequency multiplication is 1/(feedback divider). for the intermediate pll, the feedback divider is 1/45; therefore, the frequency multiplication is 45. with an input frequency of 32.768 khz, the output frequency is 1.47456 mhz. the input clock for the low-speed pll, fr, originates at the intermediate pll output. fr is multiplied by 25 to generate the 36.864-mhz clock output. amp 32kxtal2 32.768-khz crystal 32kxtal1 internal external 32 khz 32kxtal1 oscillator 32kxtal2 2 v max pin #y4
80 lan?sc400 and lansc410 microcontrollers data sheet figure 8. intermediate and low-speed plls block diagram graphics dot clock pll (lansc400 microcontroller only) the input clock to the graphics dot clock pll is the output clock (36.864 mhz) of the low-speed pll di- vided by 16. the graphics dot clock pll is not sup- ported on the lansc410 microcontroller. the output frequency is programmable using three extended reg- ister bits (pllratio[2C0]) in the range of 20.736 mhz to 36.864 mhz (spaced 2.304 mhz apart). these three bits (in graphics index register 4ch) control the output frequency by selecting the divide value in the feedback divider as shown in table 27. the graphics dot clock pll requires a stabilization period after changing frequency. figure 9 shows the block diagram for the graphics dot clock pll. phase detector down up charge pump loop filter vco vc divider reference (fr) (ff) vcca frequency feedback frequency frequency output (fo) internal external c 1 r c 2 table 27. frequency selection control for graphics dot clock pll pllratio[2C0] divider output frequency (mhz) 000 9 20.736 001 10 23.04 010 11 25.344 011 12 27.648 100 13 29.952 101 14 32.256 110 15 34.56 111 16 36.864
lan?sc400 and lansc410 microcontrollers data sheet 81 figure 9. graphics dot clock pll block diagram high-speed pll the high-speed pll generates a 66.3552-mhz clock for the dram controller. figure 10 on page 82 shows the block diagram for the high-speed pll. the input to the high-speed pll is the output of the low-speed pll divided by five. the feedback divider is nine, which results in an output frequency (fo) of 66.3552 mhz. this frequency is divided by 2 in the pmu to provide the 33-mhz input for the pll in the cpu core. band gap block the band gap reference circuit generates the bias cur- rents for the four plls and provides a 2.4-v reference source for the rtc voltage monitor. the current sources, constant over v cc , temperature, and process variations, are used by the four pll charge pumps for adjusting the pll operating frequency. the 2.4-v refer- ence voltage is used by the rtc voltage monitor to de- tect a low backup battery voltage level. rtc voltage monitor the voltage monitor for the rtc block is shown in figure 11 on page 82. its functions are to provide a reset signal to the rtc block when it detects a low backup battery voltage, and to provide an early warn- ing signal when the system is powering down. the internal rtc reset signal is asserted on power-up if the back-up battery voltage drops below 2.4 v. the one shot prevents multiple resets during power-on. an internal power-down signal is used by the rtc to isolate the rtc core from the rest of the microcontroller. the rtc voltage monitor uses the reset assertion to detect a power-down. for proper operation, reset and v cc must follow the timing in figure 12 on page 83. down up charge pump loop filter vcca 36.864 mhz phase detector vc 20.736C fo ff fr divider /16 (9C16) 36.864 mhz vco pllratio[2C0] programmable internal external c 1 r c 2
82 lan?sc400 and lansc410 microcontrollers data sheet figure 10. high-speed pll block diagram figure 11. rtc voltage monitor circuit down up charge pump loop filter vcca 36.864 mhz phase detector vc ff fr divider /5 (9) vco 66.3552 mhz fo internal external c 1 r c 2 bbatsen band gap one shot rtc reset + C internal rtc reset 32 khz d ck q flip flop power-down voltage
lan?sc400 and lansc410 microcontrollers data sheet 83 figure 12. timing diagram for rtc-on power-down sequence clock specifications the specifications for the external components re- quired to implement the four pll loop filters are shown in table 28 on page 84. table 29 on page 84 lists the electrical specifications for the analog v cc (vcca) pin. the on-chip crystal oscillator circuit supports most generic 32.768-khz crystals as long as the specification for the crystals meet the electrical parameters listed in table 30 on page 84. the worst-case start-up time required for the plls is shown in table 31 on page 84. the pll jitter specification is listed in table 32 on page 85. programmable interval timer (pit) the lansc400 and lansc410 microcontrollers are equipped with a programmable interval timer (pit) that is software-compatible with pc/at 8254 system timers. historically, the clock source for this timer has been 1.19318 mhz. however, the internal pit clock source is 1.1892 mhz. the user has two options: n use the internal pit clock source (1.1892 mhz), which can adversely affect the legacy software that depends on the 1.19318-mhz frequency. n drive an external 1.19318-mhz clock onto the clk_io pin and program this signal to be the source of the pit clock. for more details on this feature, refer to the subsection on configuring timer channel 0 in the programmable interval timer section of the lansc400 and lansc410 microcontrollers users manual , order #21030. notes: 1. these timings apply only when powering down the chip while leaving only the rtc powered. 2. applies to all v cc except for the v cc _rtc, which is left on for this mode. 3. guarantees at least one rising edge after reset before 2.7 volts is reached. reset v cc 32 khz 3.3 v 2.7 v 33 m s (min)
84 lan?sc400 and lansc410 microcontrollers data sheet table 28. loop-filter component specification for plls parameter intermediate pll low-speed pll graphics dot clock pll high-speed pll tolerance c1 0.01 m f 470 pf 470 pf 330 pf 10% c2 0.001 m f 22 pf 33 pf 15 pf 10% r4.7 k w 4.7 k w 4.7 k w 4.7 k w 10% table 29. analog v cc (vcca) specification parameter min typ max unit peak-to-peak noise on vcca 75 mv current consumption in high-speed mode 2 ma current consumption in low-speed mode 2 ma current consumption in standby mode 2 ma current consumption in suspend mode (plls off) 1 1 notes: 1. 2 ma if plls are enabled. m a table 30. 32.768-khz crystal characteristics parameter min typ max unit nominal frequency 32.768 khz load capacitance 13.5 15 16.5 pf q value 50 10 3 series resistance 60 k w insulation resistance 100 m w shunt capacitance 2.5 pf table 31. start-up time specifications plls symbol parameter min typ max unit t1 intermediate pll lock 10 ms t2 low-speed pll lock 100 m s t3 high-speed pll lock 100 m s t4 graphics dot clock pll lock 100 m s
lan?sc400 and lansc410 microcontrollers data sheet 85 figure 13. pll enabling timing sequence table 32. pll jitter specification pll min typ max unit intermediate pll frequency 1.4524 1.47456 1.4967 mhz intermediate pll cycle-to-cycle jitter 20.4 ns low-speed pll frequency 36.311 36.864 37.417 mhz low-speed pll cycle-to-cycle jitter 0.82 ns graphics dot clock pll frequency C1.5% target +1.5% mhz graphics dot clock pll cycle-to-cycle jitter 1 ns high-speed pll frequency 65.360 66.3552 67.351 mhz high-speed pll cycle-to-cycle jitter 0.5 ns t4 reset intermediate pll low-speed pll high-speed pll pllratio[2:0] graphics dot clock (wakeup) lock t1 lock t2 lock t3 pll lock
86 lan?sc400 and lansc410 microcontrollers data sheet absolute maximum ratings storage temperature . . . . . . . . . . . . C65 c to +125 c ambient temperature under bias . . C65 c to +110 c supply voltage v cc with respect to gnd . . . . . . . . . . . . . . . . . . . . . . . C0.5 v to +4.6 v voltage on 5-v-tolerant pins . . C0.5 v to (v cc +2.6 v) voltage on other pins . . . . . . . C0.5 v to (v cc +0.5 v) stresses above those listed may cause permanent device failure. functionality at or above these limits is not implied. exposure to absolute maximum ratings for extended periods may affect device reliability. operating ranges commercial (c) devices ambient temperature (t a ) operating in free air. . . . . . . . . . . . . . . .0 c to +70 c supply voltage (v cc ) . . . . . . . . . . . . +3.0 v to +3.6 v cpu voltage (v cc_ cpu) (33 & 66 mhz) +2.7 v to +3.6 v cpu voltage (v cc_ cpu) (100 mhz) +3.3 v to +3.6 v operating ranges define those limits between which the functionality of the device is guaranteed. dc characteristics over commercial and industrial operating ranges (ball grid array (bga), 33 mhz, 3.3 v) 1 notes: 1. v ccio = 3.0 vC3.6 v. for 33 and 66 mhz, t case = 0 c to +95 c (commercial). t case = C40 c to +95 c (industrial). for 100 mhz, t case = 0 c to +85 c (commercial). current out of a pin is given as a negative value. symbol parameter description min typ max unit f osc frequency of operation (internal cpu clock) 0 100 mhz p cc supply powercpu clock = 33 mhz (v cc _cpu=3.3 v) 703 879 mw p ccss 2 2. in suspend and critical suspend, the power state is the same. the plls are off, the lcd is disabled, and the cpu and all log ic are in the lowest power state. the power management unit is active. suspend power at 3.3 v and 25 c cpu idle, all internal clocks stopped except 32.768 khz 264 (80 m a) 643.5 (195 m a) m w suspend power at 3.3 v and 70 c cpu idle, all internal clocks stopped except 32.768 khz 726 (220 m a) 1950.5 (585 m a) m w p off rtc power only at 3.3 v 16 33 m w v oh(cmos) output high voltage i oh(cmos) = C0.5 ma v cc C0.45 v v ol(cmos) output low voltage i ol(cmos) = +0.5 ma 0.45 v v ih(cmos) input high voltage 2.0 3 3. v cc at 3.3 v. v cc +0.3 v v ih(5-vtol) input high voltage (5-v tolerant inputs) 2.0 3 v cc +2.5 v v il(cmos) input low voltage C0.3 +0.8 v i li input leakage current (0.1 v v out v cc ) (all pins except those with internal pullup/pulldown resistors) 10 m a i ih input leakage current (v ih = v cc C 0.1 v) (all pins with internal pulldown resistors) 60 m a i il input leakage current (v il = 0.1 v) (pins with internal pullup resistors) C60 m a i lo output leakage current (0.1 v v out v cc ) (all pins except those with internal pullup/pulldown resistors) 15 m a avcc rpCp analog v cc ripple peak to peak 100 mv
lan?sc400 and lansc410 microcontrollers data sheet 87 capacitance notes: these parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified wher e capacitance may be affected. table 33. operating voltage (commercial and industrial) power pin type 33 mhz 66 mhz 100 mhz min max min max min max analog 2.7 3.6 2.7 3.6 2.7 3.6 cpu 2.7 3.6 2.7 3.6 3.3 3.6 rtc 2.7 3.6 2.7 3.6 2.7 3.6 v cc 2.7 3.6 2.7 3.6 2.7 3.6 symbol parameter descriptions test conditions min max unit c in input capacitance f c = 1 mhz 15 pf clock capacitance 15 pf c out output capacitance 20 pf c i/o i/o pin capacitance 20 pf
88 lan?sc400 and lansc410 microcontrollers data sheet typical power numbers power requirements under different power management modes table 34 shows the maximum and typical power dissip ation for the lansc400 and lansc410 microcontrollers. table 34. power estimates power management mode (cpu clock speed) hyper-speed 1 (100 mhz) notes: 1. hyper-speed mode is defined with a cpu clock frequency of 66 or 100 mhz. there is a time penalty to engage and disengage hyper-speed mode, because a cpu stop clock/stop grant sequence is required to arbitrate the internal cpu pll start- up, cache flush, and the clearing of all internal pipelines and write buffers. the dx2 mode (66 mhz) is a clock-doubled mode with the cpu operating at 66 mhz and the rest of the system logic operating at 33 mhz. the dx4 mode (100 mhz) is a clock tripled mode with the cpu running at 100 mhz and the rest of the system running at 33 mhz. hyper-speed 1 (66 mhz) high-speed 2 (33 mhz) 2. high-speed mode is defined with a maximum cpu clock speed of 33 mhz with a 1x dynamic clock-speed change control capability. dynamic clock control allows fast, unarbitrated cpu clock-speed changes. table 34 assumes a cpu frequency of 33 mhz and that the internal lcd controller is enabled. other high-speed mode power estimates with cpu v cc = 3.3 v are shown below: cpu clock = 33 mhz/2 = 16.5 mhz, max = 601 mw, typical = 480 mw cpu clock = 33 mhz/4 = 8.25 mhz, max = 370 mw, typical = 296 mw low-speed 3 (~4 mhz) 3. low-speed mode limits the maximum cpu clock frequency to 8 mhz. table 34 assumes 8 mhz/2 = ~4.125 (cpu speed) and that the internal lcd controller is enabled. other low-speed power estimates with cpu at 3.3 v are shown below: 8 mhz/1 = 8.25 mhz, max = 370 mw, typical = 296 mw 8 mhz/4 = 2.06 mhz, max = 164 mw, typical = 132 mw standby 4 (0 mhz) 4. standby mode is defined as having the cpu idle and stopped (0 mhz), but video screen refresh continues. irq0 (dos timer irq source) is assumed to be programmed as an activity and is generated at a rate of 60 hz. this causes the pmu to tran- sition to the temporary low-speed mode where the cpu is clocked at 8 mhz. the assumed duration of the irq0 handler routine is 25 m s and, upon the interrupt return instruction, the pmu immediately re-enters the standby mode, the lcd con- troller is enabled, and dram refresh type is slow cas -before-ras . off 5 5. off is defined as the v cc _rtc supply pin having power applied and all other v cc pins are not powered. in this mode, the core cpu, power management unit, plls, etc. have no power applied. the rtc will have an internally isolated power plane and source its power from the v cc _rtc supply pin. maximum at 3.3 v 2194 mw (~665 ma) 1527 mw (~463 ma) 879 mw (~266 ma) 240 mw (~73 ma) 63 mw (~19 ma) 33 m w (10 m a) typical at 3.3 v 1818 mw (551 ma) 1222 mw (~370 ma) 703 mw (~213 ma) 192 mw (~58 ma) 50 mw (~15 ma) 16 m w (4.8 m a) maximum at 2.7 v n/a 941 mw 586 mw 144 mw 60 mw 33 m w typical at 2.7 v n/a 753 mw 469 mw 115 mw 48 mw 16 m w
lan?sc400 and lansc410 microcontrollers data sheet 89 derating curves this section describes how to use the derating curves on the following pages to determine potential specified timing variations based on system capacitive loading. the pin state tables beginning on page 42 in this doc- ument have a column named max load. this column describes the specification load presented to the spe- cific pin when testing was performed to generate the timing specification documented in the ac characteris- tics section of this data sheet. for example, to find out the effect of capacitive loading on a dram specification such as mwe hold from cas low, first find the specification load for mwe from table 7 on page 44. the value here is 70 pf. note the output drive type is programmable to c, d, or e. for this example, assume a drive strength of d, a system dram interface of 3.3 v, and a system load on the mi- crocontrollers mwe pin of 90 pf. referring to figure 20, 3.3-v i/o drive type d rise time, on page 90, a time value of approximately 8.1 ns corresponds to a capacitive load of 70 pf. also referring to figure 20, a time value of approxi- mately 10 ns corresponds to a capacitive load of 90 pf. subtracting 8.1 ns from the 10 ns, it can be seen that the rise time on the mwe signal will increase by 1.9 ns. therefore, the mwe hold from cas low (min) param- eter will increase from 30 ns to 31.9 ns (30 ns +1.9 ns). if the capacitive load on mwe had been less than 70 pf, the time given in the derating curve for the load would be subtracted from the time given for the speci- fication load. this difference can then be subtracted from the mwe hold from cas low (min) parameter to determine the derated ac timing parameter. figure 15. 3.3-v i/o drive type a fall time figure 14. 3.3-v i/o drive type a rise time 10 20 30 40 50 60 70 80 90 100 20 40 60 80 100 120 140 160 time (ns) load (pf) 10 20 30 40 50 60 70 80 90 100 20 40 60 80 100 120 140 160 time (ns) load (pf) figure 17. 3.3-v i/o drive type b fall time figure 16. 3.3-v i/o drive type b rise time 5 10 15 20 25 30 35 40 45 50 20 40 60 80 100 120 140 160 time (ns) load (pf) 5 10 15 20 25 30 35 40 45 50 20 40 60 80 100 120 140 160 time (ns) load (pf)
90 lan?sc400 and lansc410 microcontrollers data sheet figure 19. 3.3-v i/o drive type c fall time figure 18. 3.3-v i/o drive type c rise time 5 30 20 40 60 80 100 120 140 160 time (ns) load (pf) 5 10 15 20 25 30 20 40 60 80 100 120 140 160 time (ns) load (pf) 10 15 20 25 figure 21. 3.3-v i/o drive type d fall time figure 20. 3.3-v i/o drive type d rise time 2 4 6 8 10 12 14 16 18 20 40 60 80 100 120 140 160 time (ns) load (pf) 2 18 20 40 60 80 100 120 140 160 time (ns) load (pf) 4 6 8 10 12 14 16 figure 23. 3.3-v i/o drive type e fall time figure 22. 3.3-v i/o drive type e rise time 2 3 4 5 6 7 8 9 10 11 12 13 20 40 60 80 100 120 140 160 time (ns) load (pf) 2 3 4 5 6 7 8 9 10 11 12 13 20 40 60 80 100 120 140 160 time (ns) load (pf)
lan?sc400 and lansc410 microcontrollers data sheet 91 ac switching characteristics and waveforms the ac specifications provided in the ac characteris- tics tables that follow consist of output delays, input setup requirements, and input hold requirements. ac specifications measurement is defined by the figures that follow each timing table. all timings are referenced to 1.5 v unless otherwise specified. output delays are specified with minimum and maxi- mum limits, measured as shown. the minimum delay times are hold times provided to external circuitry. input setup and hold times are specified as minimums, defining the smallest acceptable sampling window. within the sampling window, a synchronous input sig- nal must be stable for correct microcontroller operation. key to switching waveforms ac switching test waveforms notes: for ac testing, inputs are driven at 3 v for a logic 1 and 0 v for a logic 0. waveforms inputs outputs must be steady will be steady may change from h to l will be changing from h to l may change from l to h will be changing from l to h dont care, any change permitted changing, state unknown does not apply center line is high-impedance "off state v cc ? 2 v cc ? 2 v ih = v cc input v il = 0 test points output
92 lan?sc400 and lansc410 microcontrollers data sheet ac switching characteristics over commercial and industrial operating ranges figure 24. power-up timing sequence table 35. power-on reset cycle symbol parameter description notes 33-mhz external bus unit min typ max t1 v cc _rtc valid hold before all other v cc s are valid 0 s t2 reset valid hold from all v cc valid (except v cc _rtc) 1 notes: 1. this parameter is dependent on the 32-khz oscillator start-up time, which is dependent on the characteristics of the crystal , leakage and capacitive coupling on the board, and ambient temperature. 0.5 s t3 v cc _rtc valid to bbatsen active 100 m s t4 cfgx setup to reset inactive 5 m s t5 cfgx hold from reset inactive 0 ns t6 rstdrv pulse width 300 ms v cc _rtc t1 all v cc s reset t2 bbatsen t3 rstdrv t6 cfgx t4 t5
lan?sc400 and lansc410 microcontrollers data sheet 93 table 36. rom/flash memory cycles symbol parameter description notes 33-mhz external bus unit min max t1 sa3Csa0 delay from sa31Csa4 6 ns t2a sa stable to romcsx assertion 1 6ns t2b sa stable to romcsx assertion when qualified with command (romrd or romwr ) 1 20 ns t2c sa stable to romcsx assertion when qualified with command (romrd or romwr ) 1 100 ns t3 romcsx deassertion to sa change 1 53 ns t4 sd setup to romrd or romcsx deassertion or burst address switching, whichever is first, for 8-/16-/32-bit device 2 15 ns t5 romwr setup to romcsx 0ns t6 data hold from sa, romrd , or romcsx change, whichever is first 2 0ns t7 romcsx pulse width 3 25 ns t8 dbufoe , r32bfoe setup to romrd , romwr low -8 ns t9 romrd pulse width 3 25 ns t10 sa3Csa0 burst address valid duration 3 25 ns t11 romwr pulse width 3 25 ns t12 sd setup to romwr assertion for 32-bit device 2 17 ns t13 sd hold from romwr deassertion 2 20 ns t14 sa hold from romwr deassertion 2 20 ns t15 romrd delay from sa stable 115 ns t16a romrd , romwr pulse width for 8-bit device 530 ns t16b romrd , romwr pulse width for 16-bit device 240 ns t17a data setup from romrd for 8-bit device 2, 4 489 ns t17b data setup from romrd for 16-bit device 2, 4 209 ns t18 romrd deassertion to sa unstable 20 ns t19 data hold from romrd deassertion 2 0ns t20 sa hold from romwr deassertion 53 ns t21a sd setup to romwr assertion for 16-bit device 2 -29 ns t21b sd setup to romwr assertion for 8-bit device 2 33 ns t22 sd hold from romwr deassertion 2 26 ns t23 iochrdy assertion to romrd , romwr deassertion 125 ns t24a iochrdy deassertion from romrd , romwr for 8-bit 378 ns t24b iochrdy deassertion from romrd , romwr for 16-bit 66 ns t25 r32bfoe /dbufoe hold from romrd high 0 ns t26 r32bfoe /dbufoe hold from romwr high 26 ns t27 dbufrdl , dbufrdh setup to romrd , romwr low -8 ns t28 dbufrdl , dbufrdh hold from romrd high 0 ns t29 dbufrdl , dbufrdh hold from romwr high 26 ns
94 lan?sc400 and lansc410 microcontrollers data sheet notes: 1. the romcsx address decode is programmable for an early decode (via bit 5 in csc index 23h, 25h, and 27h). the early address-decode is available to provide the romcsx by qualifying the address signals only; it is not qualified with the com- mands (romrd , romwr ). the timing parameter t2a pertains to the early address-decode feature being enabled (romcsx is address-decode only). parameters t2b and t2c are observed when the early address-decode feature is disabled (romcsx is address-decode qualified with command). the early decode can be enabled for both fast-mode and normal-mode rom accesses. 2. when a x32 dram or vl bus is enabled, additional delay must be added to accommodate for the delay through the external data buffers required for the sd bus in this mode. 3. there are two types of programmable wait states. the first programmable wait state is always used in the first access for either burst or non-burst supported device. it starts at the assertion of the chip select or at the transition of sa3Csa0, whic h- ever occurs later. the second programmable wait state is used only for any subsequent burst read accesses to a burst mode rom device. it starts at the transition of sa3Csa0. the burst address valid duration depends on which wait state is used. if the wait state is set to zero, then the minimum address duration is 30 ns (one bus clock cycle). 4. if wait states are added via the deassertion of iochrdy, the data setup time to iochrdy assertion is 0 ns (minimum). figure 25. fast mode 8-/16-/32-bit rom/flash memory read cycle t4 t6 t7 t7 t9 t27 t8 t9 t25 t28 t2b t6 t1 t1 sa25Csa4 sa3Csa0 romcsx romwr romrd sd15Csd0 dbufoe dbufrdl d15Cd0 (x32 rom) dbufrdh r32bfoe
lan?sc400 and lansc410 microcontrollers data sheet 95 figure 26. fast mode cpu read of three consecutive bytes from 8-bit rom/flash memory figure 27. fast mode 8-/16-/32-bit flash memory write cycles t4 t10 t6 t10 t2b 3 * t9 3 * t9 t1 t1 t2a 012 sa25Csa4 sa3Csa0 romcsx romwr romrd sd7Csd0 n otes: t he rom controller fetches the number of bytes requested by the cpu as dictated by the cpu be (byte enable) signals and r eturns the data as a single transfer. in this example, be was set to 0001. therefore, the rom controller generates additional a ddresses to read all three bytes before returning them to the cpu. t5 t11 t8 t27 t11 t13 t26 t29 t2b t14 t12 t2a sa25Csa0 romcsx romwr romrd sd15Csd0 dbufoe dbufrdl dbufrdh d15Cd0 (x32 rom) r32bfoe
96 lan?sc400 and lansc410 microcontrollers data sheet figure 28. fast mode 16-bit burst rom read cycles figure 29. fast mode cpu burst read from 32-bit burst mode rom/flash memory t10 t10 t4 t6 8 * t7 8 * t7 8 x t9 8 x t9 t2b t1 t1 t2a sa25Csa4 sa3Csa1 romcsx romwr romrd sd15Csd0 t4 t6 4 * t7 4 * t7 4 * t9 4 * t9 t2b t10 t10 t8 t27 t25 t28 t1 t1 t2a sa25Csa4 sa3Csa2 romcsx romwr romrd sd15Csd0 dbufoe dbufrdl dbufrdh r32bfoe
lan?sc400 and lansc410 microcontrollers data sheet 97 figure 30. normal mode 8-/16-bit rom/flash memory read cycles figure 31. normal mode 8-/16-bit flash memory write cycles t15 t18 t23 t16a,b t17a,b t24a,b t27 t8 t16a,b t28 t25 t2c t3 t19 t1 t1 t2a sa25Csa4 sa3Csa0 romcsx romrd romwr sd15Csd0 dbufoe iochrdy dbufrdl dbufrdh r32bfoe t16a,b t21a,b t16a,b t22 t23 t20 t8 t27 t24a,b t26 t29 t1 t1 t2a sa25Csa4 sa3Csa0 romcsx romwr romrd sd15Csd0 dbufoe dbufrdl iochrdy dbufrdh r32bfoe
98 lan?sc400 and lansc410 microcontrollers data sheet table 37. dram cycles symbol parameter description notes 33-mhz external bus unit min max t1 row address setup time 1 5ns t2 ras to cas delay 1 42.75 ns t3 row address hold time 1 14.25 ns t4 column address setup time 1 0ns t5 column address hold time 1 14.25 ns t6a cas pulse width (cpu, fast page mode) 1 42.75 ns t6a cas pulse width (graphics controller, fast page mode) 1 28.5 ns t6b cas pulse width (edo mode) 1 28.5 ns t7a cas precharge (non-interleaved) 1 14.25 ns t7b cas precharge (interleaved) 1 71.25 ns t8a cas hold 1 85.5 ns t8b cas hold (edo) 1 66.5 ns t9a fast page mode cycle time (non-interleaved) 1 57 ns t9b fast page mode cycle time (interleaved) 1 114 ns t9c edo mode cycle time 1 57 ns t10 access time from ras 1 66.5 ns t11 access time from column address 1 35 ns t12a access time from cas 1 20 ns t12b access time from cas (edo) 1 22 ns t13 access time from cas precharge 1 40 ns t14a read data hold from cas 1 0ns t14b read data hold from cas (edo) 1 5ns t15 ma12Cma0 switching time 1 15 ns t16 delay between bank cas signals 1 15 ns t17 mwe setup to cas 1 10 ns t18 mwe hold from cas 1 30 ns t19 write data setup to cas 1 10 ns t20 write data hold from cas 1 30 ns t21 ras precharge 1 60 ns t22 ras pulse width 1 75 ns t23 ras hold 1 28.5 ns t24 mwe low from cas (edo data disable) 1 14.25 ns t25 mwe pulse width (edo) 1 14.25 ns t26 data high impedance from mwe 1 15 ns t27 ras to cas precharge time 1 15 ns t28 cas setup time (cas -before-ras refresh) 1 10 ns t29 cas hold time (cas -before-ras refresh) 1 25 ns t30 ras pulse width during self-refresh cycle 1 100 us t31 ras precharge time during self-refresh cycle 1 130 ns t32 we setup time (cas -before-ras refresh) 1 25 ns t33 we hold time (cas -before-ras refresh) 1 25 ns notes: 1. all timings assume 70-ns drams, fastest programmable timing, and a 66-mhz clock for the memory controller.
lan?sc400 and lansc410 microcontrollers data sheet 99 figure 32. dram page hit read, interleaved figure 33. dram page hit write, interleaved t1 t4 t2 t6a t8a t7b t16 t6a t9b t16 t4 t6a t3 t15 t5 t15 t10 t11 t12a t14a t12a t11 ras casl3 Ccasl0 ma12Cma0 mwe d31Cd0 cash3 Ccash0 t4 t17 t19 t1 t2 t6a t8a t7b t6a t9b t16 t6a t7b t9b t6a t3 t15 t5 t15 t18 t20 t20 ras casl3 C cash3 C ma12Cma0 mwe d31Cd0 casl0 cash0
100 lan?sc400 and lansc410 microcontrollers data sheet figure 34. dram page miss read, interleaved figure 35. dram page hit read, non-interleaved t1 t4 t21 t22 t23 t2 t6a t8a t16 t6a t3 t5 t10 t11 t12a t14a t12a ras casl3 Ccasl0 cash3 Ccash0 ma12Cma0 mwe d31Cd0 t15 t1 t4 t2 t6a t8a t7a t4 t6a t9a t3 t15 t5 t15 t10 t11 t12a t12a t13 t14a ras cash3 Ccash0 ma12Cma0 mwe d31Cd0 casl3 Ccasl0
lan?sc400 and lansc410 microcontrollers data sheet 101 figure 36. dram page hit write, non-interleaved figure 37. dram page miss read, non-interleaved t1 t4 t17 t19 t2 t6a t8a t7a t6a t9a t3 t15 t15 t5 t18 t20 ras ma12Cma0 mwe d31Cd0 cash3 Ccash0 casl3 Ccasl0 t1 t4 t21 t22 t23 t2 t6a t8a t7a t6a t9a t3 t5 t15 t10 t11 t12a t14a t12a t13 ras ma12Cma0 mwe d31Cd0 cash3 Ccash0 casl3 Ccasl0 t15
102 lan?sc400 and lansc410 microcontrollers data sheet figure 38. edo dram page hit read, non-interleaved figure 39. edo dram page miss read, non-interleaved t1 t4 t2 t6b t8b t7a t6b t9c t3 t15 t5 t15 t24 t25 t10 t11 t12b t12b t13 t14b t11 t26 ras ma12Cma0 mwe d31Cd0 cash3 Ccash0 casl3 Ccasl0 notes: the edo dram page hit write timing is similar to dram page hit write timing. see figure 36 on page 101 for more information. t1 t4 t21 t22 t2 t6b t8b t3 t5 t24 t25 t10 t11 t12b t26 ras ma12Cma0 mwe d31Cd0 cash3 Ccash0 casl3 Ccasl0 notes: the edo dram page miss write timing is similar to dram page miss write timing. see figure 36 on page 101 for more information. t15
lan?sc400 and lansc410 microcontrollers data sheet 103 figure 40. dram cas -before-ras refresh figure 41. dram self-refresh t7a t28 t28 t27 t27 t27 t27 t29 t29 t29 t29 t7a t27 t27 t27 t27 t32 t22 t32 t33 t32 t33 t22 t22 t32 t33 clk_mem ras0 ras1 ras2 ras3 mwe cash3 Ccash0 casl3 Ccasl0 t28 t28 t22 t33 t7a t28 t27 7a t27 t30 t21 t31 ras mwe ss ss cash3 Ccash0 casl3 Ccasl0 notes: because the sequence shown above is performed when the microcontroller is in suspend mode, the drams must self-refresh. the ras and cas signals are held active (low) for the entire time that the microcontroller is in suspend mode. the timing diagram also shows a following cycle that brings ras and cas high again. the low period of ras and cas can be of a long duration.
104 lan?sc400 and lansc410 microcontrollers data sheet figure 42. dram slow refresh t28 t27 t7a t29 t22 t32 t33 t22 t33 t22 t33 t22 t33 ras0 ras1 ras2 ras3 mwe cash3 Ccash0 casl3 Ccasl0 notes: the diagram above shows ras and cas behavior for an lansc400 or lansc410 microcontroller running at a frequency of 16 mhz or less. in this case, the ras signals are not staggered and all are driven (low) at the same time to consume less dram bandwidth for refresh activity (consumed due to a slower clock frequency).
lan?sc400 and lansc410 microcontrollers data sheet 105 table 38. isa cycles symbol parameter description notes 33-mhz external bus unit min max t1a setup, sa, sbhe stable to command assertion, 16-bit i/o, 8-bit i/o, mem 120 ns t1b setup, sa, sbhe stable to command assertion, 16-bit mem 120 ns t2a delay, mcs16 stable from sa 102 ns t2b delay, iocs16 stable from sa 122 ns t3a pulse width, iow , 8-bit cycle 530 ns t3b pulse width, memw , 8-bit cycle 530 ns t3c pulse width, ior , 8-bit cycle 530 ns t3d pulse width, memr , 8-bit cycle 530 ns t3e pulse width, iow , 16-bit cycle 165 ns t3f pulse width, memw , 16-bit cycle 240 ns t3g pulse width, ior , 16-bit cycle 165 ns t3h pulse width, memr , 16-bit cycle 240 ns t4 sa, sbhe hold from command deassertion 53 ns t5a iochrdy delay from ior , memr , iow , memw (8-bit) 378 ns t5b iochrdy delay from ior , memr , iow , memw (16-bit) 66 ns t6 ior , memr , iow , memw delay from iochrdy 125 ns t7a ior , memr , iow , memw high time (8-bit) 187 ns t7b ior , memr , iow , memw high time (16-bit) 125 ns t8 delay, bale rising from ior , memr , iow , memw deassertion 46 ns t9 iochrdy pulse width 120 ns 15.6 m s t11a setup, sd to write command assertion, 8-bit memory, i/o write and 16-bit i/o write 33 ns t11b setup, sd to write command assertion, 16-bit memory write -29 ns t12 hold, sd from write command deassertion 30 ns t13a data access time, 8-bit read 489 ns t13b data access time, 16-bit i/o read 132 ns t13c data access time, 16-bit memory read 209 ns t14 hold, sd from read command deassertion 0 ns t15 setup, sa, sbhe stable to bale falling edge 61 ns t16 pulse width, bale 60 ns t17 setup, aen high to ior /iow assertion 145 ns t19 setup, sa, sbhe stable to command assertion 102 ns t20 hold, drq from dack assertion 0 ns t21 setup, dack assertion to i/o command assertion 145 ns t22a setup, ior assertion to memw command 235 ns t22b setup, memr command assertion to iow command 0 ns t23 delay, iochrdy assertion to command high 200 ns t24 delay, memory command to iochrdy deassertion 125 ns t25 hold, command off to dack off 60 ns t26 hold, read command off from write command off 50 ns t27 hold, aen from command off 60 ns
106 lan?sc400 and lansc410 microcontrollers data sheet t29 hold, sa, sbhe from read command 53 ns t30 setup, tc to read command deassertion 470 ns t31 hold, tc from read command deassertion 60 ns t32a pulse width, i/o write command 400 ns t32b pulse width, i/o read command 700 ns t33a pulse width, memory read command 800 ns t33b pulse width, memory write command 470 ns t34 delay, memr to valid data 272 ns t35 hold, sd from memr deassertion 11 ns t36 delay, ior to valid data 241 ns t37 hold, sd from ior deassertion 11 ns t38 setup, sd to memw assertion -21 ns t39 setup, sd to iow assertion -214 ns t41 setup, dbufrdl /dbufrdh to write command low 1 45 ns t42 hold, dbufrdl /dbufrdh from write command high 1 30 ns t43 setup, dbufrdl /dbufrdh to read command low 1 0ns t44 hold, dbufrdl /dbufrdh from read command high 1 10 ns t45 setup, dbufoe low to write command low 1 45 ns t46 hold, dbufoe from write command high 1 30 ns t47 setup, dbufoe low to read command low 1 0ns t48 hold, dbufoe from read command high 1 10 ns t49 setup, dbufrdl /dbufrdh to mem read command low, dma 1 0ns t50 hold, dbufrdl /dbufrdh from mem read command high, dma 1 10 ns t51 setup, dbufoe low to mem read command low, dma 1 0ns t52 hold, dbufoe from mem read command high, dma 1 10 ns t53 setup, dbufrdl /dbufrdh to i/o read command low, dma 1 0ns t54 setup, dbufoe low to i/o read command low, dma 1 0ns t55 hold, dbufoe from i/o read command high, dma 1 10 ns t56 hold, dbufrdl /dbufrdh from i/o read command high, dma 1 10 ns notes: 1. these parameters are applicable only when an external data transceiver is used to isolate the sd bus. table 38. isa cycles (continued) symbol parameter description notes 33-mhz external bus unit min max
lan?sc400 and lansc410 microcontrollers data sheet 107 figure 43. 8-bit isa bus cycles t1a t1a t4 t3a,b t5a t11a t41 t45 t4 t6 t5a t13a t43 t47 t6 t3c,d t12 t42 t46 t14 t44 t48 t7a t9 sa25Csa0, sbhe iow /memw ior /memr iochrdy sd7Csd0 sd7Csd0 dbufrdl dbufoe (write) (read)
108 lan?sc400 and lansc410 microcontrollers data sheet figure 44. 16-bit isa bus cycles t2a,b t1a,b t15 t2a,b t2a,b t1a,b t15 t16 t16 t16 t16 t3e,f t5b t41 t45 t11a,b t3e,f t4 t6 t47 t5b t3g,h t44 t6 t46 t14 sa25Csa0, sbhe bale iow /memw ior /memr iocs16 /mcs16 iochrdy dbufrdl dbufoe sd15Csd0 sd15Csd0 t9 dbufrdh (write) (read) t4 t42 t43 t48 t7b t13b,c
lan?sc400 and lansc410 microcontrollers data sheet 109 figure 45. isa dma read cycle t20 t21 t25 t19 t29 t17 t27 t22b t24 t32a t39 t26 t49 t51 t30 t23 t31 t35 t50 t52 pdrqx pdackx sa25Csa0, sbhe aen iow memr sd15Csd0 iochrdy tc dbufrdl dbufoe dbufrdh t32a t34 t33a
110 lan?sc400 and lansc410 microcontrollers data sheet figure 46. isa dma write cycle t20 t21 t25 t19 t29 t17 t27 t22a t24 t38 t26 t36 t30 t23 t31 t37 t56 t55 pdrqx pdackx sa23Csa0, sbhe aen memw ior sd15Csd0 iochrdy tc dbufrdl dbufoe dbufrdh t33b t53 t54 t32b
lan?sc400 and lansc410 microcontrollers data sheet 111 table 39. vesa local bus cycles symbol parameter description 33-mhz external bus unit min max t1 vl_lclk period 27 ns t2 vl_lclk pulse high 14 ns t3 vl_lclk pulse low 14 ns t4 vl_ads delay from vl_lclk 3 18 ns t5 sa25Csa2, vl_be3 Cvl_be0 , vl_m/io , vl_w/r , vl_d/c delay from vl_lclk 318ns t6 vl_blast valid from vl_lclk 3 18 ns t7 vl_ldev valid from sa25Csa2, vl_be3 Cvl_be0 , vl_m/io , vl_w/r , vl_d/c 20 ns t8 1 notes: 1. ldev is checked on the following rising edge of the cpu clock (not shown, up to 100 mhz) from the assertion of ads. ads can assert a minimum of 20 ns after address change. vl_ldev setup to vl_lclk 15 ns t9 vl_lrdy , vl_brdy setup to vl_lclk 12 ns t10 vl_lrdy , vl_brdy (vl-bus target is driver) hold from vl_lclk 0 ns t11 vl_lrdy (vl-bus target is driver) three stated from vl_lclk 0 ns t12 read data setup to vl_lclk 5 ns t13 read data hold from vl_clk 0 ns t14 write data delay from vl_clk 3 18 ns
112 lan?sc400 and lansc410 microcontrollers data sheet figure 47. vesa local bus cycles t2 t3 t9 t12 t8 t9 t12 t4 t4 t5 t5 t7 t7 t13 t13 t14 t10 t10 t11 t10 t6 t6 t6 vl_lclk cpuads 1 vl_ads s a25Csa2, vl_be vl_ldev read data write data vl_lrdy vl_brdy vl_blast notes: 1. this signal is shown as a timing reference only. it is not available as a pin on the lansc400 microcontroller. t11 t1 t14 t14
lan?sc400 and lansc410 microcontrollers data sheet 113 table 40. parallel port cycles 1 notes: 1. the signal names used in figure 48 and figure 49 are the pc/at compatible and bidirectional mode signal names. symbol parameter description notes 33-mhz external bus unit min max t1 ppdwe delay from iow 2 2. during epp mode and bidirectional mode, ppdwe acts as the parallel port chip select and is asserted for both reads and writes. for pc/at compatible mode, ppdwe will be asserted only for parallel port write cycles. 220ns t2 ppoen delay from iow 220ns t3 strb delay from iow 220ns t4 slctin , afdt valid from iow 3 3. these timings are only valid for epp mode. 220ns t5 sd setup to iow 50 ns t6 sd hold from iow 50 ns t7 busy asserted from iow asserted 4 4. busy is asserted to add wait states to the parallel port access. 300 ns t8 iow deasserted from busy deasserted 4 100 ns t9 iow pulse width 450 ns t10 slctin , afdt recovery 1000 ns t11 dbufoe setup to iow 5 5. dbufoe and dbufrdl may be required when using the vesa local bus interface or a x32 dram interface. 20 ns t12 dbufoe hold from iow 5 20 ns t13 ppdwe delay from ior 2 220ns t14 slctin , afdt valid from ior 3 220ns t15 sd setup to ior deasserted 20 ns t16 sd hold from ior 0ns t17 busy asserted from ior asserted 4 300 ns t18 ior deasserted from busy deasserted 4 100 ns t19 ior pulse width 450 ns t20 dbufoe , dbufrdl setup to ior 5 0ns t21 dbufoe , dbufrdl hold from ior 5 10 ns
114 lan?sc400 and lansc410 microcontrollers data sheet . figure 48. epp parallel port write cycle t11 t8 t5 t9 t1 t1 t2 t2 t3 t3 t4 t4 t10 t4 t4 t10 t6 t7 t12 address register access data register access iow ppdwe ppoen strb slctin afdt sd7Csd0 busy dbufoe dbufrdl
lan?sc400 and lansc410 microcontrollers data sheet 115 figure 49. epp parallel port read cycle table 41. general-purpose input/output cycles symbol parameter description 33-mhz external bus unit min max t1 sa stable to gpio_csx rising edge 10 ns t2 sa stable to gpio_csx falling edge 10 ns t3 iow rising edge to gpio_csx rising edge 5 ns t4 iow falling edge to gpio_csx falling edge 5 ns t5 ior rising edge to gpio_csx rising edge 5 ns t6 ior falling edge to gpio_csx falling edge 5 ns t7 sa stable to gpio_csx (8042cs ) falling edge 10 ns t8 sa stable to gpio_csx (8042cs ) rising edge 10 ns t9 sa stable to gpio_csx (memcs ) falling edge 10 ns t10 sa stable to gpio_csx (memcs ) rising edge 10 ns t11 memw rising edge to gpio_csx rising edge 5 ns t12 memw falling edge to gpio_csx falling edge 5 ns t13 memr rising edge to gpio_csx rising edge 5 ns t14 memr falling edge to gpio_csx falling edge 5 ns t18 t15 t19 t13 t13 t14 t14 t10 t14 t14 t10 t16 t17 t20 t21 address register access data register access ior ppdwe ppoen strb slctin afdt sd7Csd0 busy dbufoe dbufrdl
116 lan?sc400 and lansc410 microcontrollers data sheet figure 50. i/o decode (r/w), address decode only figure 51. i/o decode (r/w), command qualified t2 t1 t2 t1 sa25Csa0 gpio_csx iow ior iochrdy sd7Csd0/sd15Csd0 notes: see the isa bus section on page 105 for detailed timings between these signals. (write) (read) d7Cd0/d15Cd0 t4 t3 t6 t5 sa25Csa0 gpio_csx iow ior iochrdy notes: see the isa bus section on page 105 for detailed timings between these signals. sd7Csd0/sd15Csd0 (write) (read) sd7Csd0/sd15Csd0
lan?sc400 and lansc410 microcontrollers data sheet 117 figure 52. i/o decode (r/w), gpio_csx as 8042cs timing figure 53. memory cs decode (r/w), address decode only t7 t8 t7 t8 sa25Csa0 gpio_csx iow ior iochrdy 60h or 64h 60h or 64h notes: see the isa bus section on page 105 for detailed timings between these signals. sd7Csd0 (read) sd7Csd0 (write) t9 t10 t9 t10 sa25Csa0 gpio_csx memw memr iochrdy notes: see the isa bus section on page 105 for detailed timings between these signals. sd7Csd0 (read) sd7Csd0 (write)
118 lan?sc400 and lansc410 microcontrollers data sheet figure 54. memory cs decode (r/w), command qualified t12 t11 t14 t13 sa25Csa0 gpio_csx memw memr iochrdy notes: see the isa bus section on page 105 for detailed timings between these signals. sd7Csd0/sd15Csd0 (write) (read) sd7Csd0/sd15Csd0
lan?sc400 and lansc410 microcontrollers data sheet 119 table 42. pc card cycleslansc400 microcontroller only symbol parameter description notes 33-mhz external bus unit min max t1 reg_x , sa setup to command active 1,2 notes: 1. t is the nominal period of the selected clock: in standard mode, this is the 125-ns isa bus clock; in enhanced mode, it is t he 30-ns local bus clock. 2. s determines the setup time as programmed into the setup timing register selected from one of four timing sets. its value can be programmed to a range of 1 to 4096 ? 63. st-10 ns t2 command pulse width 1, 3 3. c determines the command active time as programmed into the command timing register selected from one of four timing sets. its value can be programmed to a range of 1 to 4096 ? 63. ct-10 ns t3 sa hold and write data valid from command inactive 1 , 4 4. r determines the recovery time as programmed into the recovery timing register selected from one of four timing sets. its value can be programmed to a range of 1 to 4096 ? 63. rt-10 ns t4 wait_ab active from command active 1, 3 (c-2)?t-10 ns t5 command hold from wait_ab inactive 1 2t ns t6 sd setup before read command inactive 1 2t+10 ns t7 sd valid from read command inactive 0 ns t8 sd valid from wait_ab inactive 1 t+10 ns t9 iois16 setup before command inactive 1 3t+10 ns t10 mceh_x delay from iois16 active 1 t-10 ns t11 iois16 delay from valid sa 35 ns t12 setup, dack assertion to dma i/o command active 145 ns t13a pulse width, dma i/o write command 220 ns t13b pulse width, dma i/o read command 700 ns t14 hold, dma i/o command inactive to dack inactive 60 ns t15 dma i/o command setup to tc active 15 ns t16 tc pulse width 62 ns t17a sd setup to dma iow active -241 ns t17b sd valid delay from dma ior active 100 ns t18a sd hold from dma iow inactive 0 ns t18b sd hold from dma ior inactive 0 ns
120 lan?sc400 and lansc410 microcontrollers data sheet figure 55. pc card attribute memory read cycle (lansc400 microcontroller only) table 43. pc card attribute memory read function (lansc400 microcontroller only) mode reg_x mceh_x mcel_x sa0 oe we sd15Csd8 sd7Csd0 byte access l l h h l l l h l l h h three-state three-state even byte not valid word access l l l indeterminate l h not valid even byte odd-byte-only access l l h indeterminate l h not valid three-state t4 t6 t7 t8 t5 t3 t1 t2 read cycle data sa25Csa0 reg_a mcel_a mceh_a oe wait_ab sd15Csd8 sd7Csd0 dbufoe dbufrdl dbufrdh reg_b mcel_b mceh_b three-state or not valid for attribute memory read cycles
lan?sc400 and lansc410 microcontrollers data sheet 121 figure 56. pc card attribute memory write cycl e (lansc400 microcontroller only) table 44. pc card attribute memory write function (lansc400 microcontroller only) mode reg_x mceh_x mcel_x sa0 oe we sd15Csd8 sd7Csd0 byte access l l h h l l l h h h l l indeterminate indeterminate even byte indeterminate word access l l l indeterminate h l indeterminate even byte odd-byte-only access l l h indeterminate h l indeterminate indeterminate t4 t5 t3 t1 t2 write cycle data not valid for attribute memory write cycles sa25Csa0 we wait_ab sd15Csd8 sd7Csd0 dbufoe dbufrdl dbufrdh reg_a mcel_a mceh_a reg_b mcel_b mceh_b
122 lan?sc400 and lansc410 microcontrollers data sheet figure 57. pc card common memory read cycle (lansc400 microcontroller only) table 45. pc card common memory read function (lansc400 microcontroller only) mode reg_x mceh_x mcel_x sa0 oe we sd15Csd8 sd7Csd0 byte access h h h h l l l h l l h h three-state three-state even byte odd byte word access h l l indeterminate l h odd byte even byte odd-byte-only access h l h indeterminate l h odd byte three-state t4 t6 t7 t8 t5 t3 t1 t2 read cycle data sa25Csa0 oe wait_ab sd15Csd0 dbufoe dbufrdl dbufrdh reg_a mcel_a mceh_a reg_b mcel_b mceh_b
lan?sc400 and lansc410 microcontrollers data sheet 123 figure 58. pc card common memory write c ycle (lansc400 microcontroller only) table 46. pc card common memory write function (lansc400 microcontroller only) mode reg_x mceh_x mcel_x sa0 oe we sd15Csd8 sd7Csd0 byte access h h h h l l l h h h l l indeterminate indeterminate even byte odd byte word access h l l indeterminate h l odd byte even byte odd-byte-only access h l h indeterminate h l odd byte indeterminate t4 t5 t3 t1 t2 write cycle data sa25Csa0 we wait_ab sd15Csd0 dbufoe dbufrdl dbufrdh reg_a mcel_a mceh_a reg_b mcel_b mceh_b
124 lan?sc400 and lansc410 microcontrollers data sheet figure 59. pc card i/o read cycle table 47. pc card i/o read function (lansc400 microcontroller only) mode reg_x mceh_x mcel_x sa0 ior iow sd15Csd8 sd7Csd0 byte access l l h h l l l h l l h h three-state three-state even byte odd byte word access l l l indeterminate l h odd byte even byte high byte only l l h indeterminate l h odd byte three-state t11 t4 t6 t7 t9 t8 t5 t3 t1 t2 t10 read cycle data sa25Csa0 ior wait_ab wp_x sd15Csd0 dbufoe dbufrdl dbufrdh (i ocs 16_x ) mceh_a mceh_b mcel_a mcel_b reg_a reg_b
lan?sc400 and lansc410 microcontrollers data sheet 125 figure 60. pc card i/o write cycle table 48. pc card i/o write function (lansc400 microcontroller only) mode reg_x mceh_x mcel_x sa0 ior iow sd15Csd8 sd7Csd0 byte access l l h h l l l h h h l l indeterminate indeterminate even byte odd byte word access l l l indeterminate h l odd byte even byte odd-byte-only access l l h indeterminate h l odd byte indeterminate t11 t4 t9 t5 t3 t1 t2 t10 write cycle data sa25Csa0 iow wait_ab sd15Csd0 dbufoe dbufrdl dbufrdh wp_x (iocs16_x ) reg_a reg_b mcel_a mcel_b mceh_a mceh_b
126 lan?sc400 and lansc410 microcontrollers data sheet figure 61. pc card dma read cycle (memory read to i/o write) table 49. pc card dma rea d function (lansc400 microcontroller only) mode dack dreq mceh_x mcel_x oe we ior iow sd15Csd8 sd7Csd0 byte access h l h l h tc h l indeterminate even byte word access h l l l h tc h l odd byte even byte t14 t12 t13a t15 t16 t17a t18a dma data to card reg_a , reg_b , mcel_a , mcel_b , oe , ior iow we (tc ) sd15Csd0 dbufoe dubfrdh dbufrdl (dack) mceh_a , mceh_b
lan?sc400 and lansc410 microcontrollers data sheet 127 figure 62. pc card dma write cycle (i/o read to memory write) table 50. pc card dma writ e function (lansc400 microcontroller only) mode dack dreq mceh_x mcel_x oe we ior iow sd15Csd8 sd7Csd0 byte access h l h l tc h l h indeterminate even byte word access h l l l tc h l h odd byte even byte t14 t12 t13b t15 t16 t17b t18b dma data from card we , iow ior oe (tc ) sd15Csd0 dbufoe dbufrdl dbufrdh reg_a , reg_b , (dack) mcel_a , mcel_b , mceh_a , mceh_b
128 lan?sc400 and lansc410 microcontrollers data sheet figure 63. graphics panel interface timing (lansc400 microcontroller only) table 51. lcd graphics controller cycleslansc400 microcontroller only symbol parameter description notes 33-mhz external bus unit min max t1a sck period, monochrome panel 1 notes: 1. t = period of internal video dot clockprogrammable via the pixel clock control register. 4t ns t1b sck period, color stn panel 2t ns t2 sck high time 1 tns t3 sck low time 1 tns t4 setup, data to sck falling edge 1 t-15 ns t5 hold, lcd_data from sck falling edge 1 t-15 ns t6 width, lc 1 8t ns t7 setup, frm to lc falling 1,2 2. programmable to within resolution of 8t intervals (single-screen mode) or 16t intervals (dual-screen mode). ns t8 hold, frm from lc falling 1,2 ns t9 delay, lc falling to m phase change 0 15 ns t11a delay, power-on sequencing, lvdd to signals 3 3. programmable through pmu control register 1, bits 2C0. 7.8 62.5 ms t11b delay, power-on sequencing, signals to lvee 4 4. programmable through pmu control register 1, bits 5C3. 7.8 62.5 ms t12a delay, power-off sequencing, lvee to signals, normal power-down 5 5. programmable through pmu control register 2, bits 2C0. 62.5 500 ms t12b delay, power-off sequencing, signals to lvdd , normal power-down 6 6. programmable through pmu control register 2, bits 5C3. 62.5 500 ms t13 delay, lvee to lcd_signals off, emergency power-down 0 ns t14 delay, lcd_signals off to lvdd off, emergency power-down 0 ns t15 delay, emergency power-off sequencing from bl2 edge 0 10 m s t2 t4 t5 t1a,b t6 t7 t8 t9 t3 sck lcdd7C lc frm m lcdd0
lan?sc400 and lansc410 microcontrollers data sheet 129 figure 64. graphics panel power seque ncing (lansc400 microcontroller only) t11a t12b t11a t15 t11b t12a t14 t13 lvdd graphics panel lvee bl2 normal operation battery failure interface signals (figure 63) t11b
130 lan?sc400 and lansc410 microcontrollers data sheet thermal characteristics the thermal specifications for the lansc400 and lansc410 microcontrollers are given as a t case (the case temperature) specification. the 33-mhz and 66-mhz devices are specified for operation when t case is with the range of 0cC+95c. the 100-mhz device is specified for operation when t case is within the range of 0cC+85c. t case can be measured in any environment to determine whether the microcon- troller is within specified operating range. the case temperature should be measured at the center of the top surface opposite the solder balls. the ambient temperature (t a ) is guaranteed as long as t case is not violated. the ambient temperature can be calculated from y j-t and q ja from the following equations: t j = t case + p ? y j-t t a = t j C p ? q ja t case = t a + p ? ( q ja C y j-t ) where: t j is the junction temperature (c). t a is the ambient temperature (c). t case is the case temperature (c). y j-t is the junction-to-case thermal resistance (c/w). q ja is the junction-to-ambient thermal resistance (c/w). p is the maximum power consumption (w). the values for q ja and y j-t are given in table 52 for the bga 292 package. these numbers are valid only for packages with all 292 balls soldered to a board with two power planes and two signal planes. table 53 shows the t a allowable (without exceeding t case ) at various airflows and operating frequencies. p is calculated using the i cc at 3.3 v as tabulated in the dc characteristics section beginning on page 86. table 52. thermal resistance y j-t and q ja (c/w) for the 292-bga package) table 53. maximum t a at various airflows in c airflow in feet/minute (m/s) thermal resistance 0 (0) 200 (1.01) 400 (2.03) 600 (3.04) 800 (4.06) q ja 25.0 20.5 19.0 18.1 17.4 y j-t 6.2 6.2 6.2 6.2 6.2 airflow in feet/minute (m/s) 0 200 400 600 800 maximum t a (0) (1.01) (2.03) (3.04) (4.06) at 33 mhz 83.7 86.4 87.3 87.8 88.3 at 66 mhz 72.0 77.5 79.3 80.4 81.3 at 100 mhz 50.8 59.0 61.7 63.4 64.6
lan?sc400 and lansc410 microcontrollers data sheet 131 physical dimensionsbga 292plastic ball grid array a1 corner a1 corner i.d. 0.50 0.70 0.51 0.61 encapsulation 4x .20 16-038-bga292-2_ab es114 9.14.98 lv side view detail a scale:none 0.15 c seating plane top side (die side) a 0.15 c 0.15 c 27.00 bsc 3x 0.50 r. b a 27.00 bsc 21.20 22.80 17.00 min 0.60 0.90 .30 .10 s c ab s c (datum b) bottom view all rows and columns 0.635 bsc 0.635 bsc 1.27 bsc 24.13 bsc a1 corner a1 corner i.d. a b c d e f g h j k l m n p r t u v w y 20 19 18 17 16 15 14 13 12 11 10 987654 32 1 24.13 bsc (datum a) 4.445 3x alignment mark 0.75 sq 3x thermal balls 2.11 2.61 c
132 lan?sc400 and lansc410 microcontrollers data sheet trademarks ? 1998 advanced micro devices, inc. all rights reserved. amd, the amd logo and combinations thereof, am186, am188, e86, k86, lan, comm86, and systems in silicon are trademarks, and am 386 and am486 are registered trademarks of advanced micro devices, inc. fusione86 is a service mark of advanced micro devices, inc. microsoft and windows are registered trademarks of microsoft corp. other product names used in this publication are for identification pu rposes and may be trademarks of their respective companies.

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